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target/m68k: add the Interrupt Stack Pointer

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Add the third stack pointer, the Interrupt Stack Pointer (ISP)
(680x0 only). This stack will be needed in softmmu mode.

Update movec to set/get the value of the three stacks.

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20180104012913.30763-17-laurent@vivier.eu>
This commit is contained in:
Laurent Vivier 2018-01-04 02:29:12 +01:00
parent b5ae1edc29
commit 6e22b28e22
7 changed files with 190 additions and 17 deletions
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70
target/m68k/cpu.h
View file

@ -89,7 +89,7 @@ typedef struct CPUM68KState {
/* SSP and USP. The current_sp is stored in aregs[7], the other here. */
int current_sp;
uint32_t sp[2];
uint32_t sp[3];
/* Condition flags. */
uint32_t cc_op;
@ -223,6 +223,74 @@ typedef enum {
#define M68K_SSP 0
#define M68K_USP 1
#define M68K_ISP 2
/* m68k Control Registers */
/* ColdFire */
/* Memory Management Control Registers */
#define M68K_CR_ASID 0x003
#define M68K_CR_ACR0 0x004
#define M68K_CR_ACR1 0x005
#define M68K_CR_ACR2 0x006
#define M68K_CR_ACR3 0x007
#define M68K_CR_MMUBAR 0x008
/* Processor Miscellaneous Registers */
#define M68K_CR_PC 0x80F
/* Local Memory and Module Control Registers */
#define M68K_CR_ROMBAR0 0xC00
#define M68K_CR_ROMBAR1 0xC01
#define M68K_CR_RAMBAR0 0xC04
#define M68K_CR_RAMBAR1 0xC05
#define M68K_CR_MPCR 0xC0C
#define M68K_CR_EDRAMBAR 0xC0D
#define M68K_CR_SECMBAR 0xC0E
#define M68K_CR_MBAR 0xC0F
/* Local Memory Address Permutation Control Registers */
#define M68K_CR_PCR1U0 0xD02
#define M68K_CR_PCR1L0 0xD03
#define M68K_CR_PCR2U0 0xD04
#define M68K_CR_PCR2L0 0xD05
#define M68K_CR_PCR3U0 0xD06
#define M68K_CR_PCR3L0 0xD07
#define M68K_CR_PCR1U1 0xD0A
#define M68K_CR_PCR1L1 0xD0B
#define M68K_CR_PCR2U1 0xD0C
#define M68K_CR_PCR2L1 0xD0D
#define M68K_CR_PCR3U1 0xD0E
#define M68K_CR_PCR3L1 0xD0F
/* MC680x0 */
/* MC680[1234]0/CPU32 */
#define M68K_CR_SFC 0x000
#define M68K_CR_DFC 0x001
#define M68K_CR_USP 0x800
#define M68K_CR_VBR 0x801 /* + Coldfire */
/* MC680[234]0 */
#define M68K_CR_CACR 0x002 /* + Coldfire */
#define M68K_CR_CAAR 0x802 /* MC68020 and MC68030 only */
#define M68K_CR_MSP 0x803
#define M68K_CR_ISP 0x804
/* MC68040/MC68LC040 */
#define M68K_CR_TC 0x003
#define M68K_CR_ITT0 0x004
#define M68K_CR_ITT1 0x005
#define M68K_CR_DTT0 0x006
#define M68K_CR_DTT1 0x007
#define M68K_CR_MMUSR 0x805
#define M68K_CR_URP 0x806
#define M68K_CR_SRP 0x807
/* MC68EC040 */
#define M68K_CR_IACR0 0x004
#define M68K_CR_IACR1 0x005
#define M68K_CR_DACR0 0x006
#define M68K_CR_DACR1 0x007
#define M68K_FPIAR_SHIFT 0
#define M68K_FPIAR (1 << M68K_FPIAR_SHIFT)