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hw/arm/aspeed_ast27x0: Add SoC Support for AST2700 A1

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The memory map for AST2700 A1 remains compatible with AST2700 A0. However, the
IRQ mapping has been updated for AST2700 A1, with GIC interrupts now ranging
from 192 to 201. Add a new IRQ map table for AST2700 A1.
Add "aspeed_soc_ast2700a1_class_init" to initialize the AST2700 A1 SoC.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-23-jamin_lin@aspeedtech.com
[ clg: Removed sc->name ]
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Jamin Lin 2025-03-07 11:59:31 +08:00 • committed by Cédric Le Goater
parent 8107448de7
commit 6de4aa8dc5
1 changed files with 79 additions and 0 deletions
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79
hw/arm/aspeed_ast27x0.c
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@ -120,6 +120,52 @@ static const int aspeed_soc_ast2700a0_irqmap[] = {
[ASPEED_DEV_SDHCI] = 133, [ASPEED_DEV_SDHCI] = 133,
}; };
static const int aspeed_soc_ast2700a1_irqmap[] = {
[ASPEED_DEV_SDMC] = 0,
[ASPEED_DEV_HACE] = 4,
[ASPEED_DEV_XDMA] = 5,
[ASPEED_DEV_UART4] = 8,
[ASPEED_DEV_SCU] = 12,
[ASPEED_DEV_RTC] = 13,
[ASPEED_DEV_EMMC] = 15,
[ASPEED_DEV_TIMER1] = 16,
[ASPEED_DEV_TIMER2] = 17,
[ASPEED_DEV_TIMER3] = 18,
[ASPEED_DEV_TIMER4] = 19,
[ASPEED_DEV_TIMER5] = 20,
[ASPEED_DEV_TIMER6] = 21,
[ASPEED_DEV_TIMER7] = 22,
[ASPEED_DEV_TIMER8] = 23,
[ASPEED_DEV_DP] = 28,
[ASPEED_DEV_LPC] = 192,
[ASPEED_DEV_IBT] = 192,
[ASPEED_DEV_KCS] = 192,
[ASPEED_DEV_I2C] = 194,
[ASPEED_DEV_ADC] = 194,
[ASPEED_DEV_GPIO] = 194,
[ASPEED_DEV_FMC] = 195,
[ASPEED_DEV_WDT] = 195,
[ASPEED_DEV_PWM] = 195,
[ASPEED_DEV_I3C] = 195,
[ASPEED_DEV_UART0] = 196,
[ASPEED_DEV_UART1] = 196,
[ASPEED_DEV_UART2] = 196,
[ASPEED_DEV_UART3] = 196,
[ASPEED_DEV_UART5] = 196,
[ASPEED_DEV_UART6] = 196,
[ASPEED_DEV_UART7] = 196,
[ASPEED_DEV_UART8] = 196,
[ASPEED_DEV_UART9] = 196,
[ASPEED_DEV_UART10] = 196,
[ASPEED_DEV_UART11] = 196,
[ASPEED_DEV_UART12] = 196,
[ASPEED_DEV_ETH1] = 196,
[ASPEED_DEV_ETH2] = 196,
[ASPEED_DEV_ETH3] = 196,
[ASPEED_DEV_PECI] = 197,
[ASPEED_DEV_SDHCI] = 197,
};
/* GICINT 128 */ /* GICINT 128 */
/* GICINT 192 */ /* GICINT 192 */
static const int ast2700_gic128_gic192_intcmap[] = { static const int ast2700_gic128_gic192_intcmap[] = {
@ -864,6 +910,33 @@ static void aspeed_soc_ast2700a0_class_init(ObjectClass *oc, void *data)
sc->get_irq = aspeed_soc_ast2700_get_irq; sc->get_irq = aspeed_soc_ast2700_get_irq;
} }
static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, void *data)
{
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-a35"),
NULL
};
DeviceClass *dc = DEVICE_CLASS(oc);
AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
/* Reason: The Aspeed SoC can only be instantiated from a board */
dc->user_creatable = false;
dc->realize = aspeed_soc_ast2700_realize;
sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST2700_A1_SILICON_REV;
sc->sram_size = 0x20000;
sc->spis_num = 3;
sc->wdts_num = 8;
sc->macs_num = 3;
sc->uarts_num = 13;
sc->num_cpus = 4;
sc->uarts_base = ASPEED_DEV_UART0;
sc->irqmap = aspeed_soc_ast2700a1_irqmap;
sc->memmap = aspeed_soc_ast2700_memmap;
sc->get_irq = aspeed_soc_ast2700_get_irq;
}
static const TypeInfo aspeed_soc_ast27x0_types[] = { static const TypeInfo aspeed_soc_ast27x0_types[] = {
{ {
.name = TYPE_ASPEED27X0_SOC, .name = TYPE_ASPEED27X0_SOC,
@ -876,6 +949,12 @@ static const TypeInfo aspeed_soc_ast27x0_types[] = {
.instance_init = aspeed_soc_ast2700_init, .instance_init = aspeed_soc_ast2700_init,
.class_init = aspeed_soc_ast2700a0_class_init, .class_init = aspeed_soc_ast2700a0_class_init,
}, },
{
.name = "ast2700-a1",
.parent = TYPE_ASPEED27X0_SOC,
.instance_init = aspeed_soc_ast2700_init,
.class_init = aspeed_soc_ast2700a1_class_init,
},
}; };
DEFINE_TYPES(aspeed_soc_ast27x0_types) DEFINE_TYPES(aspeed_soc_ast27x0_types)