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tcg/i386: Add have_atomic16

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Notice when Intel or AMD have guaranteed that vmovdqa is atomic.
The new variable will also be used in generated code.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-11-06 16:43:21 +11:00
parent e61f1efeb7
commit 6d3f2e3c64
3 changed files with 46 additions and 0 deletions
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18
include/qemu/cpuid.h
View file

@ -71,6 +71,24 @@
#define bit_LZCNT (1 << 5) #define bit_LZCNT (1 << 5)
#endif #endif
/*
* Signatures for different CPU implementations as returned from Leaf 0.
*/
#ifndef signature_INTEL_ecx
/* "Genu" "ineI" "ntel" */
#define signature_INTEL_ebx 0x756e6547
#define signature_INTEL_edx 0x49656e69
#define signature_INTEL_ecx 0x6c65746e
#endif
#ifndef signature_AMD_ecx
/* "Auth" "enti" "cAMD" */
#define signature_AMD_ebx 0x68747541
#define signature_AMD_edx 0x69746e65
#define signature_AMD_ecx 0x444d4163
#endif
static inline unsigned xgetbv_low(unsigned c) static inline unsigned xgetbv_low(unsigned c)
{ {
unsigned a, d; unsigned a, d;

27
tcg/i386/tcg-target.c.inc
View file

@ -185,6 +185,7 @@ bool have_avx512dq;
bool have_avx512vbmi2; bool have_avx512vbmi2;
bool have_avx512vl; bool have_avx512vl;
bool have_movbe; bool have_movbe;
bool have_atomic16;
#ifdef CONFIG_CPUID_H #ifdef CONFIG_CPUID_H
static bool have_bmi2; static bool have_bmi2;
@ -4026,6 +4027,32 @@ static void tcg_target_init(TCGContext *s)
have_avx512dq = (b7 & bit_AVX512DQ) != 0; have_avx512dq = (b7 & bit_AVX512DQ) != 0;
have_avx512vbmi2 = (c7 & bit_AVX512VBMI2) != 0; have_avx512vbmi2 = (c7 & bit_AVX512VBMI2) != 0;
} }
/*
* The Intel SDM has added:
* Processors that enumerate support for Intel® AVX
* (by setting the feature flag CPUID.01H:ECX.AVX[bit 28])
* guarantee that the 16-byte memory operations performed
* by the following instructions will always be carried
* out atomically:
* - MOVAPD, MOVAPS, and MOVDQA.
* - VMOVAPD, VMOVAPS, and VMOVDQA when encoded with VEX.128.
* - VMOVAPD, VMOVAPS, VMOVDQA32, and VMOVDQA64 when encoded
* with EVEX.128 and k0 (masking disabled).
* Note that these instructions require the linear addresses
* of their memory operands to be 16-byte aligned.
*
* AMD has provided an even stronger guarantee that processors
* with AVX provide 16-byte atomicity for all cachable,
* naturally aligned single loads and stores, e.g. MOVDQU.
*
* See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688
*/
if (have_avx1) {
__cpuid(0, a, b, c, d);
have_atomic16 = (c == signature_INTEL_ecx ||
c == signature_AMD_ecx);
}
} }
} }
} }

1
tcg/i386/tcg-target.h
View file

@ -120,6 +120,7 @@ extern bool have_avx512dq;
extern bool have_avx512vbmi2; extern bool have_avx512vbmi2;
extern bool have_avx512vl; extern bool have_avx512vl;
extern bool have_movbe; extern bool have_movbe;
extern bool have_atomic16;
/* optional instructions */ /* optional instructions */
#define TCG_TARGET_HAS_div2_i32 1 #define TCG_TARGET_HAS_div2_i32 1