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https://github.com/Motorhead1991/qemu.git
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rust: pl011: extract conversion to RegisterOffset
As an added bonus, this also makes the new function return u32 instead of u64, thus factoring some casts into a single place. Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini
parent
d1f27ae9ca
commit
6d314cc045
2 changed files with 79 additions and 60 deletions
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@ -5,6 +5,7 @@
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use core::ptr::{addr_of, addr_of_mut, NonNull};
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use std::{
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ffi::CStr,
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ops::ControlFlow,
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os::raw::{c_int, c_uint, c_void},
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};
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@ -222,19 +223,11 @@ impl PL011State {
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}
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}
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pub fn read(&mut self, offset: hwaddr, _size: c_uint) -> std::ops::ControlFlow<u64, u64> {
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fn regs_read(&mut self, offset: RegisterOffset) -> ControlFlow<u32, u32> {
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use RegisterOffset::*;
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let value = match RegisterOffset::try_from(offset) {
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Err(v) if (0x3f8..0x400).contains(&(v >> 2)) => {
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let device_id = self.get_class().device_id;
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u32::from(device_id[(offset - 0xfe0) >> 2])
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}
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Err(_) => {
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// qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset 0x%x\n", (int)offset);
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0
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}
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Ok(DR) => {
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ControlFlow::Break(match offset {
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DR => {
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self.flags.set_receive_fifo_full(false);
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let c = self.read_fifo[self.read_pos];
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if self.read_count > 0 {
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@ -251,69 +244,53 @@ impl PL011State {
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self.receive_status_error_clear.set_from_data(c);
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self.update();
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// Must call qemu_chr_fe_accept_input, so return Continue:
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let c = u32::from(c);
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return std::ops::ControlFlow::Continue(u64::from(c));
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return ControlFlow::Continue(u32::from(c));
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}
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Ok(RSR) => u32::from(self.receive_status_error_clear),
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Ok(FR) => u32::from(self.flags),
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Ok(FBRD) => self.fbrd,
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Ok(ILPR) => self.ilpr,
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Ok(IBRD) => self.ibrd,
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Ok(LCR_H) => u32::from(self.line_control),
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Ok(CR) => u32::from(self.control),
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Ok(FLS) => self.ifl,
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Ok(IMSC) => self.int_enabled,
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Ok(RIS) => self.int_level,
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Ok(MIS) => self.int_level & self.int_enabled,
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Ok(ICR) => {
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RSR => u32::from(self.receive_status_error_clear),
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FR => u32::from(self.flags),
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FBRD => self.fbrd,
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ILPR => self.ilpr,
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IBRD => self.ibrd,
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LCR_H => u32::from(self.line_control),
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CR => u32::from(self.control),
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FLS => self.ifl,
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IMSC => self.int_enabled,
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RIS => self.int_level,
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MIS => self.int_level & self.int_enabled,
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ICR => {
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// "The UARTICR Register is the interrupt clear register and is write-only"
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// Source: ARM DDI 0183G 3.3.13 Interrupt Clear Register, UARTICR
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0
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}
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Ok(DMACR) => self.dmacr,
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};
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std::ops::ControlFlow::Break(value.into())
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DMACR => self.dmacr,
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})
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}
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pub fn write(&mut self, offset: hwaddr, value: u64) {
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fn regs_write(&mut self, offset: RegisterOffset, value: u32) {
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// eprintln!("write offset {offset} value {value}");
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use RegisterOffset::*;
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let value: u32 = value as u32;
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match RegisterOffset::try_from(offset) {
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Err(_bad_offset) => {
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eprintln!("write bad offset {offset} value {value}");
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}
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Ok(DR) => {
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// ??? Check if transmitter is enabled.
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let ch: u8 = value as u8;
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// XXX this blocks entire thread. Rewrite to use
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// qemu_chr_fe_write and background I/O callbacks
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// SAFETY: self.char_backend is a valid CharBackend instance after it's been
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// initialized in realize().
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unsafe {
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qemu_chr_fe_write_all(addr_of_mut!(self.char_backend), &ch, 1);
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}
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match offset {
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DR => {
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self.loopback_tx(value);
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self.int_level |= registers::INT_TX;
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self.update();
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}
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Ok(RSR) => {
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self.receive_status_error_clear.reset();
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RSR => {
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self.receive_status_error_clear = 0.into();
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}
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Ok(FR) => {
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FR => {
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// flag writes are ignored
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}
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Ok(ILPR) => {
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ILPR => {
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self.ilpr = value;
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}
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Ok(IBRD) => {
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IBRD => {
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self.ibrd = value;
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}
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Ok(FBRD) => {
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FBRD => {
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self.fbrd = value;
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}
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Ok(LCR_H) => {
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LCR_H => {
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let new_val: registers::LineControl = value.into();
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// Reset the FIFO state on FIFO enable or disable
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if self.line_control.fifos_enabled() != new_val.fifos_enabled() {
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@ -336,26 +313,26 @@ impl PL011State {
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self.line_control = new_val;
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self.set_read_trigger();
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}
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Ok(CR) => {
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CR => {
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// ??? Need to implement the enable bit.
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self.control = value.into();
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self.loopback_mdmctrl();
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}
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Ok(FLS) => {
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FLS => {
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self.ifl = value;
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self.set_read_trigger();
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}
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Ok(IMSC) => {
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IMSC => {
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self.int_enabled = value;
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self.update();
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}
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Ok(RIS) => {}
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Ok(MIS) => {}
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Ok(ICR) => {
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RIS => {}
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MIS => {}
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ICR => {
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self.int_level &= !value;
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self.update();
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}
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Ok(DMACR) => {
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DMACR => {
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self.dmacr = value;
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if value & 3 > 0 {
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// qemu_log_mask(LOG_UNIMP, "pl011: DMA not implemented\n");
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@ -570,6 +547,48 @@ impl PL011State {
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Ok(())
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}
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pub fn read(&mut self, offset: hwaddr, _size: u32) -> ControlFlow<u64, u64> {
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match RegisterOffset::try_from(offset) {
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Err(v) if (0x3f8..0x400).contains(&(v >> 2)) => {
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let device_id = self.get_class().device_id;
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ControlFlow::Break(u64::from(device_id[(offset - 0xfe0) >> 2]))
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}
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Err(_) => {
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// qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset 0x%x\n", (int)offset);
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ControlFlow::Break(0)
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}
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Ok(field) => {
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let result = self.regs_read(field);
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match result {
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ControlFlow::Break(value) => ControlFlow::Break(value.into()),
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ControlFlow::Continue(value) => ControlFlow::Continue(value.into()),
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}
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}
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}
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}
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pub fn write(&mut self, offset: hwaddr, value: u64) {
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if let Ok(field) = RegisterOffset::try_from(offset) {
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// qemu_chr_fe_write_all() calls into the can_receive
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// callback, so handle writes before entering PL011Registers.
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if field == RegisterOffset::DR {
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// ??? Check if transmitter is enabled.
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let ch: u8 = value as u8;
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// SAFETY: char_backend is a valid CharBackend instance after it's been
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// initialized in realize().
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// XXX this blocks entire thread. Rewrite to use
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// qemu_chr_fe_write and background I/O callbacks
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unsafe {
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qemu_chr_fe_write_all(&mut self.char_backend, &ch, 1);
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}
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}
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self.regs_write(field, value as u32);
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} else {
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eprintln!("write bad offset {offset} value {value}");
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}
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}
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}
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/// Which bits in the interrupt status matter for each outbound IRQ line ?
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@ -43,7 +43,7 @@ pub const TYPE_PL011_LUMINARY: &::std::ffi::CStr = c_str!("pl011_luminary");
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#[doc(alias = "offset")]
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#[allow(non_camel_case_types)]
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#[repr(u64)]
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#[derive(Debug, qemu_api_macros::TryInto)]
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#[derive(Debug, Eq, PartialEq, qemu_api_macros::TryInto)]
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enum RegisterOffset {
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/// Data Register
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///
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