mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-07 17:53:56 -06:00
hw/dma/pl080: Support all three interrupt lines
The PL080 and PL081 have three outgoing interrupt lines: * DMACINTERR signals DMA errors * DMACINTTC is the DMA count interrupt * DMACINTR is a combined interrupt, the logical OR of the other two We currently only implement DMACINTR, because that's all the realview and versatile boards needed, but the instances of the PL081 in the MPS2 firmware images use all three interrupt lines. Implement the missing DMACINTERR and DMACINTTC. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
parent
aa74e355f1
commit
6d0ed6ba6c
2 changed files with 13 additions and 6 deletions
|
@ -75,11 +75,12 @@ static const unsigned char pl081_id[] =
|
|||
|
||||
static void pl080_update(PL080State *s)
|
||||
{
|
||||
if ((s->tc_int & s->tc_mask)
|
||||
|| (s->err_int & s->err_mask))
|
||||
qemu_irq_raise(s->irq);
|
||||
else
|
||||
qemu_irq_lower(s->irq);
|
||||
bool tclevel = (s->tc_int & s->tc_mask);
|
||||
bool errlevel = (s->err_int & s->err_mask);
|
||||
|
||||
qemu_set_irq(s->interr, errlevel);
|
||||
qemu_set_irq(s->inttc, tclevel);
|
||||
qemu_set_irq(s->irq, errlevel || tclevel);
|
||||
}
|
||||
|
||||
static void pl080_run(PL080State *s)
|
||||
|
@ -352,6 +353,8 @@ static void pl080_init(Object *obj)
|
|||
memory_region_init_io(&s->iomem, OBJECT(s), &pl080_ops, s, "pl080", 0x1000);
|
||||
sysbus_init_mmio(sbd, &s->iomem);
|
||||
sysbus_init_irq(sbd, &s->irq);
|
||||
sysbus_init_irq(sbd, &s->interr);
|
||||
sysbus_init_irq(sbd, &s->inttc);
|
||||
s->nchannels = 8;
|
||||
}
|
||||
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue