mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-07-29 21:33:53 -06:00
hw/nvme: rework csi handling
The controller incorrectly allows a zoned namespace to be attached even if CS.CSS is configured to only support the NVM command set for I/O queues. Rework handling of namespace command sets in general by attaching supported namespaces when the controller is started instead of, like now, statically when realized. Reviewed-by: Jesper Wendel Devantier <foss@defmacro.it> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
This commit is contained in:
Klaus Jensen
parent
d96a32de3f
commit
6ccca4b6bb
4 changed files with 131 additions and 111 deletions
213
hw/nvme/ctrl.c
213
hw/nvme/ctrl.c
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@ -277,15 +277,14 @@ static const uint32_t nvme_cse_acs_default[256] = {
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[NVME_ADM_CMD_SET_FEATURES] = NVME_CMD_EFF_CSUPP,
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[NVME_ADM_CMD_GET_FEATURES] = NVME_CMD_EFF_CSUPP,
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[NVME_ADM_CMD_ASYNC_EV_REQ] = NVME_CMD_EFF_CSUPP,
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[NVME_ADM_CMD_NS_ATTACHMENT] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_NIC,
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[NVME_ADM_CMD_NS_ATTACHMENT] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_NIC |
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NVME_CMD_EFF_CCC,
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[NVME_ADM_CMD_FORMAT_NVM] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
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[NVME_ADM_CMD_DIRECTIVE_RECV] = NVME_CMD_EFF_CSUPP,
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[NVME_ADM_CMD_DIRECTIVE_SEND] = NVME_CMD_EFF_CSUPP,
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};
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static const uint32_t nvme_cse_iocs_none[256];
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static const uint32_t nvme_cse_iocs_nvm[256] = {
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static const uint32_t nvme_cse_iocs_nvm_default[256] = {
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[NVME_CMD_FLUSH] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
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[NVME_CMD_WRITE_ZEROES] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
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[NVME_CMD_WRITE] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
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@ -298,7 +297,7 @@ static const uint32_t nvme_cse_iocs_nvm[256] = {
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[NVME_CMD_IO_MGMT_SEND] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
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};
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static const uint32_t nvme_cse_iocs_zoned[256] = {
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static const uint32_t nvme_cse_iocs_zoned_default[256] = {
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[NVME_CMD_FLUSH] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
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[NVME_CMD_WRITE_ZEROES] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
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[NVME_CMD_WRITE] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
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@ -307,6 +306,9 @@ static const uint32_t nvme_cse_iocs_zoned[256] = {
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[NVME_CMD_VERIFY] = NVME_CMD_EFF_CSUPP,
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[NVME_CMD_COPY] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
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[NVME_CMD_COMPARE] = NVME_CMD_EFF_CSUPP,
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[NVME_CMD_IO_MGMT_RECV] = NVME_CMD_EFF_CSUPP,
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[NVME_CMD_IO_MGMT_SEND] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
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[NVME_CMD_ZONE_APPEND] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
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[NVME_CMD_ZONE_MGMT_SEND] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
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[NVME_CMD_ZONE_MGMT_RECV] = NVME_CMD_EFF_CSUPP,
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@ -4603,6 +4605,61 @@ static uint16_t nvme_io_mgmt_send(NvmeCtrl *n, NvmeRequest *req)
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};
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}
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static uint16_t __nvme_io_cmd_nvm(NvmeCtrl *n, NvmeRequest *req)
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{
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switch (req->cmd.opcode) {
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case NVME_CMD_WRITE:
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return nvme_write(n, req);
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case NVME_CMD_READ:
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return nvme_read(n, req);
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case NVME_CMD_COMPARE:
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return nvme_compare(n, req);
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case NVME_CMD_WRITE_ZEROES:
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return nvme_write_zeroes(n, req);
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case NVME_CMD_DSM:
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return nvme_dsm(n, req);
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case NVME_CMD_VERIFY:
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return nvme_verify(n, req);
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case NVME_CMD_COPY:
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return nvme_copy(n, req);
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case NVME_CMD_IO_MGMT_RECV:
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return nvme_io_mgmt_recv(n, req);
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case NVME_CMD_IO_MGMT_SEND:
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return nvme_io_mgmt_send(n, req);
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}
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g_assert_not_reached();
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}
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static uint16_t nvme_io_cmd_nvm(NvmeCtrl *n, NvmeRequest *req)
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{
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if (!(n->cse.iocs.nvm[req->cmd.opcode] & NVME_CMD_EFF_CSUPP)) {
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trace_pci_nvme_err_invalid_opc(req->cmd.opcode);
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return NVME_INVALID_OPCODE | NVME_DNR;
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}
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return __nvme_io_cmd_nvm(n, req);
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}
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static uint16_t nvme_io_cmd_zoned(NvmeCtrl *n, NvmeRequest *req)
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{
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if (!(n->cse.iocs.zoned[req->cmd.opcode] & NVME_CMD_EFF_CSUPP)) {
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trace_pci_nvme_err_invalid_opc(req->cmd.opcode);
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return NVME_INVALID_OPCODE | NVME_DNR;
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}
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switch (req->cmd.opcode) {
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case NVME_CMD_ZONE_APPEND:
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return nvme_zone_append(n, req);
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case NVME_CMD_ZONE_MGMT_SEND:
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return nvme_zone_mgmt_send(n, req);
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case NVME_CMD_ZONE_MGMT_RECV:
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return nvme_zone_mgmt_recv(n, req);
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}
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return __nvme_io_cmd_nvm(n, req);
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}
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static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeRequest *req)
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{
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NvmeNamespace *ns;
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@ -4644,11 +4701,6 @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeRequest *req)
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return NVME_INVALID_FIELD | NVME_DNR;
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}
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if (!(ns->iocs[req->cmd.opcode] & NVME_CMD_EFF_CSUPP)) {
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trace_pci_nvme_err_invalid_opc(req->cmd.opcode);
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return NVME_INVALID_OPCODE | NVME_DNR;
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}
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if (ns->status) {
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return ns->status;
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}
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@ -4659,36 +4711,14 @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeRequest *req)
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req->ns = ns;
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switch (req->cmd.opcode) {
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case NVME_CMD_WRITE_ZEROES:
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return nvme_write_zeroes(n, req);
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case NVME_CMD_ZONE_APPEND:
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return nvme_zone_append(n, req);
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case NVME_CMD_WRITE:
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return nvme_write(n, req);
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case NVME_CMD_READ:
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return nvme_read(n, req);
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case NVME_CMD_COMPARE:
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return nvme_compare(n, req);
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case NVME_CMD_DSM:
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return nvme_dsm(n, req);
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case NVME_CMD_VERIFY:
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return nvme_verify(n, req);
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case NVME_CMD_COPY:
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return nvme_copy(n, req);
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case NVME_CMD_ZONE_MGMT_SEND:
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return nvme_zone_mgmt_send(n, req);
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case NVME_CMD_ZONE_MGMT_RECV:
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return nvme_zone_mgmt_recv(n, req);
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case NVME_CMD_IO_MGMT_RECV:
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return nvme_io_mgmt_recv(n, req);
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case NVME_CMD_IO_MGMT_SEND:
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return nvme_io_mgmt_send(n, req);
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default:
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g_assert_not_reached();
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switch (ns->csi) {
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case NVME_CSI_NVM:
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return nvme_io_cmd_nvm(n, req);
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case NVME_CSI_ZONED:
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return nvme_io_cmd_zoned(n, req);
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}
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return NVME_INVALID_OPCODE | NVME_DNR;
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g_assert_not_reached();
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}
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static void nvme_cq_notifier(EventNotifier *e)
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@ -5147,7 +5177,7 @@ static uint16_t nvme_cmd_effects(NvmeCtrl *n, uint8_t csi, uint32_t buf_len,
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uint64_t off, NvmeRequest *req)
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{
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NvmeEffectsLog log = {};
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const uint32_t *src_iocs = NULL;
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const uint32_t *iocs = NULL;
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uint32_t trans_len;
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if (off >= sizeof(log)) {
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@ -5157,25 +5187,26 @@ static uint16_t nvme_cmd_effects(NvmeCtrl *n, uint8_t csi, uint32_t buf_len,
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switch (NVME_CC_CSS(ldl_le_p(&n->bar.cc))) {
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case NVME_CC_CSS_NVM:
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src_iocs = nvme_cse_iocs_nvm;
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/* fall through */
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case NVME_CC_CSS_ADMIN_ONLY:
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iocs = n->cse.iocs.nvm;
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break;
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case NVME_CC_CSS_CSI:
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case NVME_CC_CSS_ALL:
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switch (csi) {
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case NVME_CSI_NVM:
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src_iocs = nvme_cse_iocs_nvm;
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iocs = n->cse.iocs.nvm;
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break;
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case NVME_CSI_ZONED:
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src_iocs = nvme_cse_iocs_zoned;
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iocs = n->cse.iocs.zoned;
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break;
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}
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break;
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}
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memcpy(log.acs, n->cse.acs, sizeof(log.acs));
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if (src_iocs) {
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memcpy(log.iocs, src_iocs, sizeof(log.iocs));
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if (iocs) {
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memcpy(log.iocs, iocs, sizeof(log.iocs));
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}
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trans_len = MIN(sizeof(log) - off, buf_len);
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@ -6718,25 +6749,29 @@ static void nvme_update_dsm_limits(NvmeCtrl *n, NvmeNamespace *ns)
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}
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}
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static void nvme_select_iocs_ns(NvmeCtrl *n, NvmeNamespace *ns)
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static bool nvme_csi_supported(NvmeCtrl *n, uint8_t csi)
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{
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uint32_t cc = ldl_le_p(&n->bar.cc);
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uint32_t cc;
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ns->iocs = nvme_cse_iocs_none;
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switch (ns->csi) {
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switch (csi) {
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case NVME_CSI_NVM:
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if (NVME_CC_CSS(cc) != NVME_CC_CSS_ADMIN_ONLY) {
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ns->iocs = nvme_cse_iocs_nvm;
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}
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break;
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return true;
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case NVME_CSI_ZONED:
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if (NVME_CC_CSS(cc) == NVME_CC_CSS_CSI) {
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ns->iocs = nvme_cse_iocs_zoned;
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} else if (NVME_CC_CSS(cc) == NVME_CC_CSS_NVM) {
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ns->iocs = nvme_cse_iocs_nvm;
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}
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break;
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cc = ldl_le_p(&n->bar.cc);
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return NVME_CC_CSS(cc) == NVME_CC_CSS_ALL;
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}
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g_assert_not_reached();
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}
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static void nvme_detach_ns(NvmeCtrl *n, NvmeNamespace *ns)
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{
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assert(ns->attached > 0);
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n->namespaces[ns->params.nsid] = NULL;
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ns->attached--;
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}
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static uint16_t nvme_ns_attachment(NvmeCtrl *n, NvmeRequest *req)
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@ -6781,7 +6816,7 @@ static uint16_t nvme_ns_attachment(NvmeCtrl *n, NvmeRequest *req)
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switch (sel) {
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case NVME_NS_ATTACHMENT_ATTACH:
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if (nvme_ns(ctrl, nsid)) {
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if (nvme_ns(n, nsid)) {
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return NVME_NS_ALREADY_ATTACHED | NVME_DNR;
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}
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@ -6789,19 +6824,17 @@ static uint16_t nvme_ns_attachment(NvmeCtrl *n, NvmeRequest *req)
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return NVME_NS_PRIVATE | NVME_DNR;
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}
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if (!nvme_csi_supported(n, ns->csi)) {
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return NVME_IOCS_NOT_SUPPORTED | NVME_DNR;
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}
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nvme_attach_ns(ctrl, ns);
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nvme_select_iocs_ns(ctrl, ns);
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nvme_update_dsm_limits(ctrl, ns);
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break;
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case NVME_NS_ATTACHMENT_DETACH:
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if (!nvme_ns(ctrl, nsid)) {
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return NVME_NS_NOT_ATTACHED | NVME_DNR;
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}
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ctrl->namespaces[nsid] = NULL;
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ns->attached--;
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nvme_detach_ns(ctrl, ns);
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nvme_update_dsm_limits(ctrl, NULL);
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break;
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@ -7652,21 +7685,6 @@ static void nvme_ctrl_shutdown(NvmeCtrl *n)
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}
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}
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static void nvme_select_iocs(NvmeCtrl *n)
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{
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NvmeNamespace *ns;
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int i;
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for (i = 1; i <= NVME_MAX_NAMESPACES; i++) {
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ns = nvme_ns(n, i);
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if (!ns) {
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continue;
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}
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nvme_select_iocs_ns(n, ns);
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}
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}
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static int nvme_start_ctrl(NvmeCtrl *n)
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{
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uint64_t cap = ldq_le_p(&n->bar.cap);
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@ -7733,7 +7751,18 @@ static int nvme_start_ctrl(NvmeCtrl *n)
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nvme_set_timestamp(n, 0ULL);
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nvme_select_iocs(n);
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/* verify that the command sets of attached namespaces are supported */
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for (int i = 1; i <= NVME_MAX_NAMESPACES; i++) {
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NvmeNamespace *ns = nvme_subsys_ns(n->subsys, i);
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if (ns && nvme_csi_supported(n, ns->csi) && !ns->params.detached) {
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if (!ns->attached || ns->params.shared) {
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nvme_attach_ns(n, ns);
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}
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}
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}
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nvme_update_dsm_limits(n, NULL);
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return 0;
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}
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@ -8748,6 +8777,9 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
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uint16_t oacs;
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memcpy(n->cse.acs, nvme_cse_acs_default, sizeof(n->cse.acs));
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memcpy(n->cse.iocs.nvm, nvme_cse_iocs_nvm_default, sizeof(n->cse.iocs.nvm));
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memcpy(n->cse.iocs.zoned, nvme_cse_iocs_zoned_default,
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sizeof(n->cse.iocs.zoned));
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id->vid = cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID));
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id->ssvid = cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID));
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@ -8859,9 +8891,8 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
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NVME_CAP_SET_MQES(cap, n->params.mqes);
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NVME_CAP_SET_CQR(cap, 1);
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NVME_CAP_SET_TO(cap, 0xf);
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NVME_CAP_SET_CSS(cap, NVME_CAP_CSS_NVM);
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NVME_CAP_SET_CSS(cap, NVME_CAP_CSS_CSI_SUPP);
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NVME_CAP_SET_CSS(cap, NVME_CAP_CSS_ADMIN_ONLY);
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NVME_CAP_SET_CSS(cap, NVME_CAP_CSS_NCSS);
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NVME_CAP_SET_CSS(cap, NVME_CAP_CSS_IOCSS);
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NVME_CAP_SET_MPSMAX(cap, 4);
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NVME_CAP_SET_CMBS(cap, n->params.cmb_size_mb ? 1 : 0);
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NVME_CAP_SET_PMRS(cap, n->pmr.dev ? 1 : 0);
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@ -8908,8 +8939,6 @@ void nvme_attach_ns(NvmeCtrl *n, NvmeNamespace *ns)
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n->namespaces[nsid] = ns;
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ns->attached++;
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nvme_update_dsm_limits(n, ns);
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}
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static void nvme_realize(PCIDevice *pci_dev, Error **errp)
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@ -8965,7 +8994,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp)
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return;
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}
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nvme_attach_ns(n, ns);
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n->subsys->namespaces[ns->params.nsid] = ns;
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}
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}
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14
hw/nvme/ns.c
14
hw/nvme/ns.c
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@ -763,20 +763,6 @@ static void nvme_ns_realize(DeviceState *dev, Error **errp)
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ns->id_ns.endgid = cpu_to_le16(0x1);
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ns->id_ns_ind.endgrpid = cpu_to_le16(0x1);
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if (ns->params.detached) {
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return;
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}
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if (ns->params.shared) {
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for (i = 0; i < ARRAY_SIZE(subsys->ctrls); i++) {
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NvmeCtrl *ctrl = subsys->ctrls[i];
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if (ctrl && ctrl != SUBSYS_SLOT_RSVD) {
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nvme_attach_ns(ctrl, ns);
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}
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}
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}
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}
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static const Property nvme_ns_props[] = {
|
||||
|
|
|
|||
|
|
@ -237,7 +237,6 @@ typedef struct NvmeNamespace {
|
|||
NvmeLBAF lbaf;
|
||||
unsigned int nlbaf;
|
||||
size_t lbasz;
|
||||
const uint32_t *iocs;
|
||||
uint8_t csi;
|
||||
uint16_t status;
|
||||
int attached;
|
||||
|
|
@ -587,6 +586,10 @@ typedef struct NvmeCtrl {
|
|||
|
||||
struct {
|
||||
uint32_t acs[256];
|
||||
struct {
|
||||
uint32_t nvm[256];
|
||||
uint32_t zoned[256];
|
||||
} iocs;
|
||||
} cse;
|
||||
|
||||
struct {
|
||||
|
|
|
|||
|
|
@ -142,9 +142,9 @@ enum NvmeCapMask {
|
|||
((cap) |= (uint64_t)((val) & CAP_CMBS_MASK) << CAP_CMBS_SHIFT)
|
||||
|
||||
enum NvmeCapCss {
|
||||
NVME_CAP_CSS_NVM = 1 << 0,
|
||||
NVME_CAP_CSS_CSI_SUPP = 1 << 6,
|
||||
NVME_CAP_CSS_ADMIN_ONLY = 1 << 7,
|
||||
NVME_CAP_CSS_NCSS = 1 << 0,
|
||||
NVME_CAP_CSS_IOCSS = 1 << 6,
|
||||
NVME_CAP_CSS_NOIOCSS = 1 << 7,
|
||||
};
|
||||
|
||||
enum NvmeCcShift {
|
||||
|
|
@ -177,7 +177,7 @@ enum NvmeCcMask {
|
|||
|
||||
enum NvmeCcCss {
|
||||
NVME_CC_CSS_NVM = 0x0,
|
||||
NVME_CC_CSS_CSI = 0x6,
|
||||
NVME_CC_CSS_ALL = 0x6,
|
||||
NVME_CC_CSS_ADMIN_ONLY = 0x7,
|
||||
};
|
||||
|
||||
|
|
@ -938,6 +938,8 @@ enum NvmeStatusCodes {
|
|||
NVME_INVALID_SEC_CTRL_STATE = 0x0120,
|
||||
NVME_INVALID_NUM_RESOURCES = 0x0121,
|
||||
NVME_INVALID_RESOURCE_ID = 0x0122,
|
||||
NVME_IOCS_NOT_SUPPORTED = 0x0129,
|
||||
NVME_IOCS_NOT_ENABLED = 0x012a,
|
||||
NVME_IOCS_COMBINATION_REJECTED = 0x012b,
|
||||
NVME_INVALID_IOCS = 0x012c,
|
||||
NVME_CONFLICTING_ATTRS = 0x0180,
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue