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target-arm: Add registers for PMSAv7
Define the arm CP registers for PMSAv7 and their accessor functions. RGNR serves as a shared index that indexes into arrays storing the DRBAR, DRSR and DRACR registers. DRBAR and friends have to be VMSDd separately from the CP interface using a new PMSA specific VMSD subsection. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 172cf135fbd8f5cea413c00e71cc1c3cac704744.1434501320.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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3281af8114
commit
6cb0b013a1
4 changed files with 133 additions and 7 deletions
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@ -125,6 +125,39 @@ static const VMStateDescription vmstate_thumb2ee = {
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}
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};
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static bool pmsav7_needed(void *opaque)
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{
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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return arm_feature(env, ARM_FEATURE_MPU) &&
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arm_feature(env, ARM_FEATURE_V7);
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}
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static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id)
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{
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ARMCPU *cpu = opaque;
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return cpu->env.cp15.c6_rgnr < cpu->pmsav7_dregion;
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}
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static const VMStateDescription vmstate_pmsav7 = {
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.name = "cpu/pmsav7",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = pmsav7_needed,
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.fields = (VMStateField[]) {
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VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0,
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vmstate_info_uint32, uint32_t),
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VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0,
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vmstate_info_uint32, uint32_t),
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VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0,
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vmstate_info_uint32, uint32_t),
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VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate),
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VMSTATE_END_OF_LIST()
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}
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};
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static int get_cpsr(QEMUFile *f, void *opaque, size_t size)
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{
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ARMCPU *cpu = opaque;
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@ -291,6 +324,7 @@ const VMStateDescription vmstate_arm_cpu = {
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&vmstate_iwmmxt,
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&vmstate_m,
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&vmstate_thumb2ee,
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&vmstate_pmsav7,
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NULL
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}
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};
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