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target/riscv: Merge argument decode for RVC shifti

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Special handling for IMM==0 is the only difference between
RVC shifti and RVI shifti.  This can be handled with !function.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Richard Henderson 2019-04-01 10:11:51 +07:00 • committed by Palmer Dabbelt
parent e1d455dd91
commit 6cafec92f1
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3 changed files with 12 additions and 53 deletions
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6
target/riscv/translate.c
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@ -558,6 +558,12 @@ static int ex_rvc_register(DisasContext *ctx, int reg)
return 8 + reg;
}
static int ex_rvc_shifti(DisasContext *ctx, int imm)
{
/* For RV128 a shamt of 0 means a shift by 64. */
return imm ? imm : 64;
}
/* Include the auto-generated decoder for 32 bit insn */
#include "decode_insn32.inc.c"