motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-09-09 00:07:57 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

tcg: Merge INDEX_op_shl_{i32,i64}

Browse source 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-01-07 21:50:04 -08:00
parent 27d21ee7c7
commit 6ca594517a
7 changed files with 17 additions and 25 deletions
Download patch file Download diff file Expand all files Collapse all files

4
docs/devel/tcg-ops.rst
View file

@ -379,10 +379,10 @@ Shifts/Rotates
.. list-table::
* - shl_i32/i64 *t0*, *t1*, *t2*
* - shl *t0*, *t1*, *t2*
- | *t0* = *t1* << *t2*
| Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64)
| Unspecified behavior for negative or out-of-range shifts.
* - shr_i32/i64 *t0*, *t1*, *t2*

3
include/tcg/tcg-opc.h
View file

@ -58,6 +58,7 @@ DEF(or, 1, 2, 0, TCG_OPF_INT)
DEF(orc, 1, 2, 0, TCG_OPF_INT)
DEF(rems, 1, 2, 0, TCG_OPF_INT)
DEF(remu, 1, 2, 0, TCG_OPF_INT)
DEF(shl, 1, 2, 0, TCG_OPF_INT)
DEF(sub, 1, 2, 0, TCG_OPF_INT)
DEF(xor, 1, 2, 0, TCG_OPF_INT)
@ -74,7 +75,6 @@ DEF(st8_i32, 0, 2, 1, 0)
DEF(st16_i32, 0, 2, 1, 0)
DEF(st_i32, 0, 2, 1, 0)
/* shifts/rotates */
DEF(shl_i32, 1, 2, 0, 0)
DEF(shr_i32, 1, 2, 0, 0)
DEF(sar_i32, 1, 2, 0, 0)
DEF(rotl_i32, 1, 2, 0, 0)
@ -115,7 +115,6 @@ DEF(st16_i64, 0, 2, 1, 0)
DEF(st32_i64, 0, 2, 1, 0)
DEF(st_i64, 0, 2, 1, 0)
/* shifts/rotates */
DEF(shl_i64, 1, 2, 0, 0)
DEF(shr_i64, 1, 2, 0, 0)
DEF(sar_i64, 1, 2, 0, 0)
DEF(rotl_i64, 1, 2, 0, 0)

8
tcg/optimize.c
View file

@ -446,10 +446,10 @@ static uint64_t do_constant_folding_2(TCGOpcode op, TCGType type,
case INDEX_op_xor_vec:
return x ^ y;
case INDEX_op_shl_i32:
case INDEX_op_shl:
if (type == TCG_TYPE_I32) {
return (uint32_t)x << (y & 31);
case INDEX_op_shl_i64:
}
return (uint64_t)x << (y & 63);
case INDEX_op_shr_i32:
@ -3031,7 +3031,7 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(rotl):
CASE_OP_32_64(rotr):
CASE_OP_32_64(sar):
CASE_OP_32_64(shl):
case INDEX_op_shl:
CASE_OP_32_64(shr):
done = fold_shift(&ctx, op);
break;

4
tcg/tcg-op.c
View file

@ -481,7 +481,7 @@ void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
tcg_gen_op3_i32(INDEX_op_shl, ret, arg1, arg2);
}
void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
@ -1606,7 +1606,7 @@ void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
{
if (TCG_TARGET_REG_BITS == 64) {
tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
tcg_gen_op3_i64(INDEX_op_shl, ret, arg1, arg2);
} else {
gen_helper_shl_i64(ret, arg1, arg2);
}

6
tcg/tcg.c
View file

@ -1042,8 +1042,7 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
OUTOP(INDEX_op_orc, TCGOutOpBinary, outop_orc),
OUTOP(INDEX_op_rems, TCGOutOpBinary, outop_rems),
OUTOP(INDEX_op_remu, TCGOutOpBinary, outop_remu),
OUTOP(INDEX_op_shl_i32, TCGOutOpBinary, outop_shl),
OUTOP(INDEX_op_shl_i64, TCGOutOpBinary, outop_shl),
OUTOP(INDEX_op_shl, TCGOutOpBinary, outop_shl),
OUTOP(INDEX_op_sub, TCGOutOpSubtract, outop_sub),
OUTOP(INDEX_op_xor, TCGOutOpBinary, outop_xor),
};
@ -5423,8 +5422,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
case INDEX_op_orc:
case INDEX_op_rems:
case INDEX_op_remu:
case INDEX_op_shl_i32:
case INDEX_op_shl_i64:
case INDEX_op_shl:
case INDEX_op_xor:
{
const TCGOutOpBinary *out =

13
tcg/tci.c
View file

@ -615,11 +615,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break;
#endif
/* Shift/rotate operations (32 bit). */
/* Shift/rotate operations. */
case INDEX_op_shl_i32:
case INDEX_op_shl:
tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = (uint32_t)regs[r1] << (regs[r2] & 31);
regs[r0] = regs[r1] << (regs[r2] % TCG_TARGET_REG_BITS);
break;
case INDEX_op_shr_i32:
tci_args_rrr(insn, &r0, &r1, &r2);
@ -787,10 +787,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
/* Shift/rotate operations (64 bit). */
case INDEX_op_shl_i64:
tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] << (regs[r2] & 63);
break;
case INDEX_op_shr_i64:
tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] >> (regs[r2] & 63);
@ -1081,10 +1077,9 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_orc:
case INDEX_op_rems:
case INDEX_op_remu:
case INDEX_op_shl:
case INDEX_op_sub:
case INDEX_op_xor:
case INDEX_op_shl_i32:
case INDEX_op_shl_i64:
case INDEX_op_shr_i32:
case INDEX_op_shr_i64:
case INDEX_op_sar_i32:

2
tcg/tci/tcg-target.c.inc
View file

@ -779,7 +779,7 @@ static const TCGOutOpBinary outop_remu = {
static void tgen_shl(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_op_rrr(s, glue(INDEX_op_shl_i,TCG_TARGET_REG_BITS), a0, a1, a2);
tcg_out_op_rrr(s, INDEX_op_shl, a0, a1, a2);
}
static const TCGOutOpBinary outop_shl = {