mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-05 00:33:55 -06:00
x86: implement la57 paging mode
The new paging more is extension of IA32e mode with more additional page table level. It brings support of 57-bit vitrual address space (128PB) and 52-bit physical address space (4PB). The structure of new page table level is identical to pml4. The feature is enumerated with CPUID.(EAX=07H, ECX=0):ECX[bit 16]. CR4.LA57[bit 12] need to be set when pageing enables to activate 5-level paging mode. Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Message-Id: <20161215001305.146807-1-kirill.shutemov@linux.intel.com> [Drop changes to target-i386/translate.c. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Kirill A. Shutemov
Paolo Bonzini
parent
c52ab08aee
commit
6c7c3c21f9
5 changed files with 274 additions and 74 deletions
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@ -30,13 +30,18 @@
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#include "hmp.h"
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static void print_pte(Monitor *mon, hwaddr addr,
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hwaddr pte,
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hwaddr mask)
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static void print_pte(Monitor *mon, CPUArchState *env, hwaddr addr,
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hwaddr pte, hwaddr mask)
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{
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#ifdef TARGET_X86_64
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if (addr & (1ULL << 47)) {
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addr |= -1LL << 48;
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if (env->cr[4] & CR4_LA57_MASK) {
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if (addr & (1ULL << 56)) {
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addr |= -1LL << 57;
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}
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} else {
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if (addr & (1ULL << 47)) {
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addr |= -1LL << 48;
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}
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}
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#endif
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monitor_printf(mon, TARGET_FMT_plx ": " TARGET_FMT_plx
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@ -66,13 +71,13 @@ static void tlb_info_32(Monitor *mon, CPUArchState *env)
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if (pde & PG_PRESENT_MASK) {
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if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
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/* 4M pages */
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print_pte(mon, (l1 << 22), pde, ~((1 << 21) - 1));
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print_pte(mon, env, (l1 << 22), pde, ~((1 << 21) - 1));
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} else {
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for(l2 = 0; l2 < 1024; l2++) {
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cpu_physical_memory_read((pde & ~0xfff) + l2 * 4, &pte, 4);
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pte = le32_to_cpu(pte);
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if (pte & PG_PRESENT_MASK) {
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print_pte(mon, (l1 << 22) + (l2 << 12),
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print_pte(mon, env, (l1 << 22) + (l2 << 12),
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pte & ~PG_PSE_MASK,
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~0xfff);
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}
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@ -100,7 +105,7 @@ static void tlb_info_pae32(Monitor *mon, CPUArchState *env)
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if (pde & PG_PRESENT_MASK) {
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if (pde & PG_PSE_MASK) {
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/* 2M pages with PAE, CR4.PSE is ignored */
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print_pte(mon, (l1 << 30 ) + (l2 << 21), pde,
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print_pte(mon, env, (l1 << 30) + (l2 << 21), pde,
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~((hwaddr)(1 << 20) - 1));
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} else {
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pt_addr = pde & 0x3fffffffff000ULL;
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@ -108,7 +113,7 @@ static void tlb_info_pae32(Monitor *mon, CPUArchState *env)
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cpu_physical_memory_read(pt_addr + l3 * 8, &pte, 8);
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pte = le64_to_cpu(pte);
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if (pte & PG_PRESENT_MASK) {
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print_pte(mon, (l1 << 30 ) + (l2 << 21)
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print_pte(mon, env, (l1 << 30) + (l2 << 21)
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+ (l3 << 12),
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pte & ~PG_PSE_MASK,
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~(hwaddr)0xfff);
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@ -122,61 +127,82 @@ static void tlb_info_pae32(Monitor *mon, CPUArchState *env)
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}
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#ifdef TARGET_X86_64
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static void tlb_info_64(Monitor *mon, CPUArchState *env)
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static void tlb_info_la48(Monitor *mon, CPUArchState *env,
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uint64_t l0, uint64_t pml4_addr)
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{
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uint64_t l1, l2, l3, l4;
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uint64_t pml4e, pdpe, pde, pte;
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uint64_t pml4_addr, pdp_addr, pd_addr, pt_addr;
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uint64_t pdp_addr, pd_addr, pt_addr;
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pml4_addr = env->cr[3] & 0x3fffffffff000ULL;
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for (l1 = 0; l1 < 512; l1++) {
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cpu_physical_memory_read(pml4_addr + l1 * 8, &pml4e, 8);
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pml4e = le64_to_cpu(pml4e);
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if (pml4e & PG_PRESENT_MASK) {
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pdp_addr = pml4e & 0x3fffffffff000ULL;
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for (l2 = 0; l2 < 512; l2++) {
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cpu_physical_memory_read(pdp_addr + l2 * 8, &pdpe, 8);
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pdpe = le64_to_cpu(pdpe);
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if (pdpe & PG_PRESENT_MASK) {
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if (pdpe & PG_PSE_MASK) {
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/* 1G pages, CR4.PSE is ignored */
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print_pte(mon, (l1 << 39) + (l2 << 30), pdpe,
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0x3ffffc0000000ULL);
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} else {
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pd_addr = pdpe & 0x3fffffffff000ULL;
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for (l3 = 0; l3 < 512; l3++) {
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cpu_physical_memory_read(pd_addr + l3 * 8, &pde, 8);
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pde = le64_to_cpu(pde);
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if (pde & PG_PRESENT_MASK) {
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if (pde & PG_PSE_MASK) {
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/* 2M pages, CR4.PSE is ignored */
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print_pte(mon, (l1 << 39) + (l2 << 30) +
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(l3 << 21), pde,
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0x3ffffffe00000ULL);
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} else {
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pt_addr = pde & 0x3fffffffff000ULL;
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for (l4 = 0; l4 < 512; l4++) {
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cpu_physical_memory_read(pt_addr
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+ l4 * 8,
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&pte, 8);
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pte = le64_to_cpu(pte);
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if (pte & PG_PRESENT_MASK) {
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print_pte(mon, (l1 << 39) +
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(l2 << 30) +
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(l3 << 21) + (l4 << 12),
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pte & ~PG_PSE_MASK,
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0x3fffffffff000ULL);
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}
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}
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}
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}
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}
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if (!(pml4e & PG_PRESENT_MASK)) {
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continue;
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}
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pdp_addr = pml4e & 0x3fffffffff000ULL;
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for (l2 = 0; l2 < 512; l2++) {
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cpu_physical_memory_read(pdp_addr + l2 * 8, &pdpe, 8);
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pdpe = le64_to_cpu(pdpe);
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if (!(pdpe & PG_PRESENT_MASK)) {
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continue;
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}
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if (pdpe & PG_PSE_MASK) {
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/* 1G pages, CR4.PSE is ignored */
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print_pte(mon, env, (l0 << 48) + (l1 << 39) + (l2 << 30),
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pdpe, 0x3ffffc0000000ULL);
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continue;
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}
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pd_addr = pdpe & 0x3fffffffff000ULL;
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for (l3 = 0; l3 < 512; l3++) {
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cpu_physical_memory_read(pd_addr + l3 * 8, &pde, 8);
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pde = le64_to_cpu(pde);
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if (!(pde & PG_PRESENT_MASK)) {
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continue;
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}
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if (pde & PG_PSE_MASK) {
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/* 2M pages, CR4.PSE is ignored */
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print_pte(mon, env, (l0 << 48) + (l1 << 39) + (l2 << 30) +
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(l3 << 21), pde, 0x3ffffffe00000ULL);
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continue;
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}
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pt_addr = pde & 0x3fffffffff000ULL;
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for (l4 = 0; l4 < 512; l4++) {
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cpu_physical_memory_read(pt_addr
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+ l4 * 8,
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&pte, 8);
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pte = le64_to_cpu(pte);
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if (pte & PG_PRESENT_MASK) {
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print_pte(mon, env, (l0 << 48) + (l1 << 39) +
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(l2 << 30) + (l3 << 21) + (l4 << 12),
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pte & ~PG_PSE_MASK, 0x3fffffffff000ULL);
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}
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}
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}
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}
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}
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}
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static void tlb_info_la57(Monitor *mon, CPUArchState *env)
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{
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uint64_t l0;
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uint64_t pml5e;
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uint64_t pml5_addr;
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pml5_addr = env->cr[3] & 0x3fffffffff000ULL;
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for (l0 = 0; l0 < 512; l0++) {
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cpu_physical_memory_read(pml5_addr + l0 * 8, &pml5e, 8);
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pml5e = le64_to_cpu(pml5e);
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if (pml5e & PG_PRESENT_MASK) {
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tlb_info_la48(mon, env, l0, pml5e & 0x3fffffffff000ULL);
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}
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}
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}
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#endif /* TARGET_X86_64 */
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void hmp_info_tlb(Monitor *mon, const QDict *qdict)
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@ -192,7 +218,11 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict)
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if (env->cr[4] & CR4_PAE_MASK) {
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#ifdef TARGET_X86_64
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if (env->hflags & HF_LMA_MASK) {
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tlb_info_64(mon, env);
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if (env->cr[4] & CR4_LA57_MASK) {
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tlb_info_la57(mon, env);
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} else {
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tlb_info_la48(mon, env, 0, env->cr[3] & 0x3fffffffff000ULL);
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}
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} else
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#endif
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{
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@ -324,7 +354,7 @@ static void mem_info_pae32(Monitor *mon, CPUArchState *env)
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#ifdef TARGET_X86_64
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static void mem_info_64(Monitor *mon, CPUArchState *env)
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static void mem_info_la48(Monitor *mon, CPUArchState *env)
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{
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int prot, last_prot;
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uint64_t l1, l2, l3, l4;
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@ -400,6 +430,98 @@ static void mem_info_64(Monitor *mon, CPUArchState *env)
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/* Flush last range */
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mem_print(mon, &start, &last_prot, (hwaddr)1 << 48, 0);
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}
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static void mem_info_la57(Monitor *mon, CPUArchState *env)
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{
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int prot, last_prot;
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uint64_t l0, l1, l2, l3, l4;
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uint64_t pml5e, pml4e, pdpe, pde, pte;
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uint64_t pml5_addr, pml4_addr, pdp_addr, pd_addr, pt_addr, start, end;
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pml5_addr = env->cr[3] & 0x3fffffffff000ULL;
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last_prot = 0;
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start = -1;
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for (l0 = 0; l0 < 512; l0++) {
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cpu_physical_memory_read(pml5_addr + l0 * 8, &pml5e, 8);
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pml4e = le64_to_cpu(pml5e);
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end = l0 << 48;
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if (!(pml5e & PG_PRESENT_MASK)) {
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prot = 0;
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mem_print(mon, &start, &last_prot, end, prot);
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continue;
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}
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pml4_addr = pml5e & 0x3fffffffff000ULL;
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for (l1 = 0; l1 < 512; l1++) {
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cpu_physical_memory_read(pml4_addr + l1 * 8, &pml4e, 8);
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pml4e = le64_to_cpu(pml4e);
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end = (l0 << 48) + (l1 << 39);
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if (!(pml4e & PG_PRESENT_MASK)) {
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prot = 0;
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mem_print(mon, &start, &last_prot, end, prot);
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continue;
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}
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pdp_addr = pml4e & 0x3fffffffff000ULL;
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for (l2 = 0; l2 < 512; l2++) {
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cpu_physical_memory_read(pdp_addr + l2 * 8, &pdpe, 8);
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pdpe = le64_to_cpu(pdpe);
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end = (l0 << 48) + (l1 << 39) + (l2 << 30);
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if (pdpe & PG_PRESENT_MASK) {
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prot = 0;
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mem_print(mon, &start, &last_prot, end, prot);
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continue;
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}
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if (pdpe & PG_PSE_MASK) {
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prot = pdpe & (PG_USER_MASK | PG_RW_MASK |
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PG_PRESENT_MASK);
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prot &= pml4e;
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mem_print(mon, &start, &last_prot, end, prot);
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continue;
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}
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pd_addr = pdpe & 0x3fffffffff000ULL;
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for (l3 = 0; l3 < 512; l3++) {
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cpu_physical_memory_read(pd_addr + l3 * 8, &pde, 8);
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pde = le64_to_cpu(pde);
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end = (l0 << 48) + (l1 << 39) + (l2 << 30) + (l3 << 21);
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if (pde & PG_PRESENT_MASK) {
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prot = 0;
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mem_print(mon, &start, &last_prot, end, prot);
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continue;
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}
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if (pde & PG_PSE_MASK) {
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prot = pde & (PG_USER_MASK | PG_RW_MASK |
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PG_PRESENT_MASK);
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prot &= pml4e & pdpe;
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mem_print(mon, &start, &last_prot, end, prot);
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continue;
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}
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pt_addr = pde & 0x3fffffffff000ULL;
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for (l4 = 0; l4 < 512; l4++) {
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cpu_physical_memory_read(pt_addr + l4 * 8, &pte, 8);
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pte = le64_to_cpu(pte);
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end = (l0 << 48) + (l1 << 39) + (l2 << 30) +
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(l3 << 21) + (l4 << 12);
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if (pte & PG_PRESENT_MASK) {
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prot = pte & (PG_USER_MASK | PG_RW_MASK |
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PG_PRESENT_MASK);
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prot &= pml4e & pdpe & pde;
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} else {
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prot = 0;
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}
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mem_print(mon, &start, &last_prot, end, prot);
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}
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}
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}
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}
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}
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/* Flush last range */
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mem_print(mon, &start, &last_prot, (hwaddr)1 << 57, 0);
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}
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#endif /* TARGET_X86_64 */
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void hmp_info_mem(Monitor *mon, const QDict *qdict)
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@ -415,7 +537,11 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
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if (env->cr[4] & CR4_PAE_MASK) {
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#ifdef TARGET_X86_64
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if (env->hflags & HF_LMA_MASK) {
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mem_info_64(mon, env);
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if (env->cr[4] & CR4_LA57_MASK) {
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mem_info_la57(mon, env);
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} else {
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mem_info_la48(mon, env);
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}
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} else
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#endif
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{
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