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Hexagon (target/hexagon) decide if pred has been written at TCG gen time
Multiple writes to the same preg are and'ed together. Rather than generating a runtime check, we can determine at TCG generation time if the predicate has previously been written in the packet. Test added to tests/tcg/hexagon/misc.c Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-7-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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743debbc37
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5 changed files with 44 additions and 10 deletions
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@ -172,6 +172,7 @@ static void gen_start_packet(DisasContext *ctx, Packet *pkt)
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ctx->reg_log_idx = 0;
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bitmap_zero(ctx->regs_written, TOTAL_PER_THREAD_REGS);
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ctx->preg_log_idx = 0;
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bitmap_zero(ctx->pregs_written, NUM_PREGS);
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for (i = 0; i < STORES_MAX; i++) {
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ctx->store_width[i] = 0;
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}
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@ -226,7 +227,7 @@ static void mark_implicit_pred_write(DisasContext *ctx, Insn *insn,
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}
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}
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static void mark_implicit_writes(DisasContext *ctx, Insn *insn)
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static void mark_implicit_reg_writes(DisasContext *ctx, Insn *insn)
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{
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mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_FP, HEX_REG_FP);
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mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SP, HEX_REG_SP);
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@ -235,7 +236,10 @@ static void mark_implicit_writes(DisasContext *ctx, Insn *insn)
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mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA0, HEX_REG_SA0);
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mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LC1, HEX_REG_LC1);
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mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA1, HEX_REG_SA1);
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}
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static void mark_implicit_pred_writes(DisasContext *ctx, Insn *insn)
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{
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mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P0, 0);
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mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P1, 1);
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mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P2, 2);
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@ -246,8 +250,9 @@ static void gen_insn(CPUHexagonState *env, DisasContext *ctx,
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Insn *insn, Packet *pkt)
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{
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if (insn->generate) {
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mark_implicit_writes(ctx, insn);
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mark_implicit_reg_writes(ctx, insn);
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insn->generate(env, ctx, insn, pkt);
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mark_implicit_pred_writes(ctx, insn);
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} else {
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gen_exception_end_tb(ctx, HEX_EXCP_INVALID_OPCODE);
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}
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