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target/nios2: Remove the deprecated Nios II target
The Nios II target is deprecated since v8.2 in commit 9997771bc1
("target/nios2: Deprecate the Nios II architecture").
Remove:
- Buildsys / CI infra
- User emulation
- System emulation (10m50-ghrd & nios2-generic-nommu machines)
- Tests
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Marek Vasut <marex@denx.de>
Message-Id: <20240327144806.11319-3-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé
parent
92360d6e62
commit
6c3014858c
85 changed files with 31 additions and 8949 deletions
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@ -87,9 +87,6 @@ config GOLDFISH_PIC
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config M68K_IRQC
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bool
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config NIOS2_VIC
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bool
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config LOONGARCH_IPI
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bool
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@ -68,7 +68,6 @@ specific_ss.add(when: 'CONFIG_XIVE', if_true: files('xive.c'))
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specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'],
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if_true: files('spapr_xive_kvm.c'))
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specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
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specific_ss.add(when: 'CONFIG_NIOS2_VIC', if_true: files('nios2_vic.c'))
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specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: files('loongarch_ipi.c'))
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specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c'))
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specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarch_pch_msi.c'))
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@ -1,313 +0,0 @@
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/*
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* Vectored Interrupt Controller for nios2 processor
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*
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* Copyright (c) 2022 Neuroblade
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*
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* Interface:
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* QOM property "cpu": link to the Nios2 CPU (must be set)
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* Unnamed GPIO inputs 0..NIOS2_VIC_MAX_IRQ-1: input IRQ lines
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* IRQ should be connected to nios2 IRQ0.
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*
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* Reference: "Embedded Peripherals IP User Guide
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* for Intel® Quartus® Prime Design Suite: 21.4"
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* Chapter 38 "Vectored Interrupt Controller Core"
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* See: https://www.intel.com/content/www/us/en/docs/programmable/683130/21-4/vectored-interrupt-controller-core.html
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "qapi/error.h"
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#include "qemu/bitops.h"
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#include "qemu/log.h"
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#include "qom/object.h"
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#include "hw/intc/nios2_vic.h"
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#include "cpu.h"
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enum {
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INT_CONFIG0 = 0,
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INT_CONFIG31 = 31,
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INT_ENABLE = 32,
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INT_ENABLE_SET = 33,
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INT_ENABLE_CLR = 34,
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INT_PENDING = 35,
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INT_RAW_STATUS = 36,
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SW_INTERRUPT = 37,
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SW_INTERRUPT_SET = 38,
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SW_INTERRUPT_CLR = 39,
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VIC_CONFIG = 40,
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VIC_STATUS = 41,
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VEC_TBL_BASE = 42,
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VEC_TBL_ADDR = 43,
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CSR_COUNT /* Last! */
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};
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/* Requested interrupt level (INT_CONFIG[0:5]) */
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static inline uint32_t vic_int_config_ril(const Nios2VIC *vic, int irq_num)
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{
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return extract32(vic->int_config[irq_num], 0, 6);
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}
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/* Requested NMI (INT_CONFIG[6]) */
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static inline uint32_t vic_int_config_rnmi(const Nios2VIC *vic, int irq_num)
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{
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return extract32(vic->int_config[irq_num], 6, 1);
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}
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/* Requested register set (INT_CONFIG[7:12]) */
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static inline uint32_t vic_int_config_rrs(const Nios2VIC *vic, int irq_num)
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{
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return extract32(vic->int_config[irq_num], 7, 6);
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}
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static inline uint32_t vic_config_vec_size(const Nios2VIC *vic)
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{
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return 1 << (2 + extract32(vic->vic_config, 0, 3));
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}
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static inline uint32_t vic_int_pending(const Nios2VIC *vic)
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{
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return (vic->int_raw_status | vic->sw_int) & vic->int_enable;
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}
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static void vic_update_irq(Nios2VIC *vic)
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{
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Nios2CPU *cpu = NIOS2_CPU(vic->cpu);
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uint32_t pending = vic_int_pending(vic);
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int irq = -1;
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int max_ril = 0;
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/* Note that if RIL is 0 for an interrupt it is effectively disabled */
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vic->vec_tbl_addr = 0;
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vic->vic_status = 0;
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if (pending == 0) {
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qemu_irq_lower(vic->output_int);
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return;
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}
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for (int i = 0; i < NIOS2_VIC_MAX_IRQ; i++) {
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if (pending & BIT(i)) {
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int ril = vic_int_config_ril(vic, i);
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if (ril > max_ril) {
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irq = i;
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max_ril = ril;
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}
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}
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}
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if (irq < 0) {
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qemu_irq_lower(vic->output_int);
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return;
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}
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vic->vec_tbl_addr = irq * vic_config_vec_size(vic) + vic->vec_tbl_base;
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vic->vic_status = irq | BIT(31);
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/*
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* In hardware, the interface between the VIC and the CPU is via the
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* External Interrupt Controller interface, where the interrupt controller
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* presents the CPU with a packet of data containing:
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* - Requested Handler Address (RHA): 32 bits
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* - Requested Register Set (RRS) : 6 bits
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* - Requested Interrupt Level (RIL) : 6 bits
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* - Requested NMI flag (RNMI) : 1 bit
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* In our emulation, we implement this by writing the data directly to
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* fields in the CPU object and then raising the IRQ line to tell
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* the CPU that we've done so.
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*/
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cpu->rha = vic->vec_tbl_addr;
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cpu->ril = max_ril;
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cpu->rrs = vic_int_config_rrs(vic, irq);
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cpu->rnmi = vic_int_config_rnmi(vic, irq);
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qemu_irq_raise(vic->output_int);
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}
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static void vic_set_irq(void *opaque, int irq_num, int level)
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{
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Nios2VIC *vic = opaque;
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vic->int_raw_status = deposit32(vic->int_raw_status, irq_num, 1, !!level);
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vic_update_irq(vic);
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}
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static void nios2_vic_reset(DeviceState *dev)
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{
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Nios2VIC *vic = NIOS2_VIC(dev);
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memset(&vic->int_config, 0, sizeof(vic->int_config));
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vic->vic_config = 0;
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vic->int_raw_status = 0;
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vic->int_enable = 0;
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vic->sw_int = 0;
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vic->vic_status = 0;
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vic->vec_tbl_base = 0;
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vic->vec_tbl_addr = 0;
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}
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static uint64_t nios2_vic_csr_read(void *opaque, hwaddr offset, unsigned size)
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{
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Nios2VIC *vic = opaque;
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int index = offset / 4;
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switch (index) {
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case INT_CONFIG0 ... INT_CONFIG31:
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return vic->int_config[index - INT_CONFIG0];
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case INT_ENABLE:
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return vic->int_enable;
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case INT_PENDING:
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return vic_int_pending(vic);
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case INT_RAW_STATUS:
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return vic->int_raw_status;
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case SW_INTERRUPT:
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return vic->sw_int;
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case VIC_CONFIG:
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return vic->vic_config;
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case VIC_STATUS:
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return vic->vic_status;
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case VEC_TBL_BASE:
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return vic->vec_tbl_base;
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case VEC_TBL_ADDR:
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return vic->vec_tbl_addr;
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default:
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return 0;
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}
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}
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static void nios2_vic_csr_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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Nios2VIC *vic = opaque;
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int index = offset / 4;
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switch (index) {
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case INT_CONFIG0 ... INT_CONFIG31:
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vic->int_config[index - INT_CONFIG0] = value;
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break;
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case INT_ENABLE:
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vic->int_enable = value;
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break;
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case INT_ENABLE_SET:
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vic->int_enable |= value;
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break;
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case INT_ENABLE_CLR:
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vic->int_enable &= ~value;
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break;
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case SW_INTERRUPT:
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vic->sw_int = value;
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break;
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case SW_INTERRUPT_SET:
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vic->sw_int |= value;
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break;
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case SW_INTERRUPT_CLR:
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vic->sw_int &= ~value;
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break;
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case VIC_CONFIG:
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vic->vic_config = value;
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break;
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case VEC_TBL_BASE:
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vic->vec_tbl_base = value;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"nios2-vic: write to invalid CSR address %#"
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HWADDR_PRIx "\n", offset);
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}
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vic_update_irq(vic);
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}
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static const MemoryRegionOps nios2_vic_csr_ops = {
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.read = nios2_vic_csr_read,
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.write = nios2_vic_csr_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = { .min_access_size = 4, .max_access_size = 4 }
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};
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static void nios2_vic_realize(DeviceState *dev, Error **errp)
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{
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Nios2VIC *vic = NIOS2_VIC(dev);
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if (!vic->cpu) {
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/* This is a programming error in the code using this device */
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error_setg(errp, "nios2-vic 'cpu' link property was not set");
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return;
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}
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sysbus_init_irq(SYS_BUS_DEVICE(dev), &vic->output_int);
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qdev_init_gpio_in(dev, vic_set_irq, NIOS2_VIC_MAX_IRQ);
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memory_region_init_io(&vic->csr, OBJECT(dev), &nios2_vic_csr_ops, vic,
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"nios2.vic.csr", CSR_COUNT * sizeof(uint32_t));
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sysbus_init_mmio(SYS_BUS_DEVICE(dev), &vic->csr);
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}
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static Property nios2_vic_properties[] = {
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DEFINE_PROP_LINK("cpu", Nios2VIC, cpu, TYPE_CPU, CPUState *),
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DEFINE_PROP_END_OF_LIST()
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};
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static const VMStateDescription nios2_vic_vmstate = {
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.name = "nios2-vic",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (const VMStateField[]){
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VMSTATE_UINT32_ARRAY(int_config, Nios2VIC, 32),
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VMSTATE_UINT32(vic_config, Nios2VIC),
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VMSTATE_UINT32(int_raw_status, Nios2VIC),
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VMSTATE_UINT32(int_enable, Nios2VIC),
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VMSTATE_UINT32(sw_int, Nios2VIC),
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VMSTATE_UINT32(vic_status, Nios2VIC),
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VMSTATE_UINT32(vec_tbl_base, Nios2VIC),
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VMSTATE_UINT32(vec_tbl_addr, Nios2VIC),
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VMSTATE_END_OF_LIST()
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},
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};
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static void nios2_vic_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = nios2_vic_reset;
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dc->realize = nios2_vic_realize;
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dc->vmsd = &nios2_vic_vmstate;
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device_class_set_props(dc, nios2_vic_properties);
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}
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static const TypeInfo nios2_vic_info = {
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.name = TYPE_NIOS2_VIC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(Nios2VIC),
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.class_init = nios2_vic_class_init,
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};
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static void nios2_vic_register_types(void)
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{
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type_register_static(&nios2_vic_info);
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}
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type_init(nios2_vic_register_types);
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