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target/riscv: support for 128-bit shift instructions

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Handling shifts for 32, 64 and 128 operation length for RV128, following the
general framework for handling various olens proposed by Richard.

Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-13-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frédéric Pétrot 2022-01-06 22:01:02 +01:00 • committed by Alistair Francis
parent 57c108b864
commit 6bf4bbed20
4 changed files with 270 additions and 44 deletions
Download patch file Download diff file Expand all files Collapse all files

224
target/riscv/insn_trans/trans_rvi.c.inc
View file

@ -353,9 +353,22 @@ static bool trans_andi(DisasContext *ctx, arg_andi *a)
return gen_logic_imm_fn(ctx, a, tcg_gen_andi_tl);
}
static void gen_slli_i128(TCGv retl, TCGv reth,
TCGv src1l, TCGv src1h,
target_long shamt)
{
if (shamt >= 64) {
tcg_gen_shli_tl(reth, src1l, shamt - 64);
tcg_gen_movi_tl(retl, 0);
} else {
tcg_gen_extract2_tl(reth, src1l, src1h, 64 - shamt);
tcg_gen_shli_tl(retl, src1l, shamt);
}
}
static bool trans_slli(DisasContext *ctx, arg_slli *a)
{
return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl, gen_slli_i128);
}
static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
@ -363,10 +376,23 @@ static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
tcg_gen_extract_tl(dst, src, shamt, 32 - shamt);
}
static void gen_srli_i128(TCGv retl, TCGv reth,
TCGv src1l, TCGv src1h,
target_long shamt)
{
if (shamt >= 64) {
tcg_gen_shri_tl(retl, src1h, shamt - 64);
tcg_gen_movi_tl(reth, 0);
} else {
tcg_gen_extract2_tl(retl, src1l, src1h, shamt);
tcg_gen_shri_tl(reth, src1h, shamt);
}
}
static bool trans_srli(DisasContext *ctx, arg_srli *a)
{
return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
tcg_gen_shri_tl, gen_srliw);
tcg_gen_shri_tl, gen_srliw, gen_srli_i128);
}
static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
@ -374,10 +400,23 @@ static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt);
}
static void gen_srai_i128(TCGv retl, TCGv reth,
TCGv src1l, TCGv src1h,
target_long shamt)
{
if (shamt >= 64) {
tcg_gen_sari_tl(retl, src1h, shamt - 64);
tcg_gen_sari_tl(reth, src1h, 63);
} else {
tcg_gen_extract2_tl(retl, src1l, src1h, shamt);
tcg_gen_sari_tl(reth, src1h, shamt);
}
}
static bool trans_srai(DisasContext *ctx, arg_srai *a)
{
return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
tcg_gen_sari_tl, gen_sraiw);
tcg_gen_sari_tl, gen_sraiw, gen_srai_i128);
}
static bool trans_add(DisasContext *ctx, arg_add *a)
@ -390,9 +429,44 @@ static bool trans_sub(DisasContext *ctx, arg_sub *a)
return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl);
}
static void gen_sll_i128(TCGv destl, TCGv desth,
TCGv src1l, TCGv src1h, TCGv shamt)
{
TCGv ls = tcg_temp_new();
TCGv rs = tcg_temp_new();
TCGv hs = tcg_temp_new();
TCGv ll = tcg_temp_new();
TCGv lr = tcg_temp_new();
TCGv h0 = tcg_temp_new();
TCGv h1 = tcg_temp_new();
TCGv zero = tcg_constant_tl(0);
tcg_gen_andi_tl(hs, shamt, 64);
tcg_gen_andi_tl(ls, shamt, 63);
tcg_gen_neg_tl(shamt, shamt);
tcg_gen_andi_tl(rs, shamt, 63);
tcg_gen_shl_tl(ll, src1l, ls);
tcg_gen_shl_tl(h0, src1h, ls);
tcg_gen_shr_tl(lr, src1l, rs);
tcg_gen_movcond_tl(TCG_COND_NE, lr, shamt, zero, lr, zero);
tcg_gen_or_tl(h1, h0, lr);
tcg_gen_movcond_tl(TCG_COND_NE, destl, hs, zero, zero, ll);
tcg_gen_movcond_tl(TCG_COND_NE, desth, hs, zero, ll, h1);
tcg_temp_free(ls);
tcg_temp_free(rs);
tcg_temp_free(hs);
tcg_temp_free(ll);
tcg_temp_free(lr);
tcg_temp_free(h0);
tcg_temp_free(h1);
}
static bool trans_sll(DisasContext *ctx, arg_sll *a)
{
return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl);
return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl, gen_sll_i128);
}
static bool trans_slt(DisasContext *ctx, arg_slt *a)
@ -405,14 +479,85 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
return gen_arith(ctx, a, EXT_SIGN, gen_sltu);
}
static void gen_srl_i128(TCGv destl, TCGv desth,
TCGv src1l, TCGv src1h, TCGv shamt)
{
TCGv ls = tcg_temp_new();
TCGv rs = tcg_temp_new();
TCGv hs = tcg_temp_new();
TCGv ll = tcg_temp_new();
TCGv lr = tcg_temp_new();
TCGv h0 = tcg_temp_new();
TCGv h1 = tcg_temp_new();
TCGv zero = tcg_constant_tl(0);
tcg_gen_andi_tl(hs, shamt, 64);
tcg_gen_andi_tl(rs, shamt, 63);
tcg_gen_neg_tl(shamt, shamt);
tcg_gen_andi_tl(ls, shamt, 63);
tcg_gen_shr_tl(lr, src1l, rs);
tcg_gen_shr_tl(h1, src1h, rs);
tcg_gen_shl_tl(ll, src1h, ls);
tcg_gen_movcond_tl(TCG_COND_NE, ll, shamt, zero, ll, zero);
tcg_gen_or_tl(h0, ll, lr);
tcg_gen_movcond_tl(TCG_COND_NE, destl, hs, zero, h1, h0);
tcg_gen_movcond_tl(TCG_COND_NE, desth, hs, zero, zero, h1);
tcg_temp_free(ls);
tcg_temp_free(rs);
tcg_temp_free(hs);
tcg_temp_free(ll);
tcg_temp_free(lr);
tcg_temp_free(h0);
tcg_temp_free(h1);
}
static bool trans_srl(DisasContext *ctx, arg_srl *a)
{
return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl);
return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl, gen_srl_i128);
}
static void gen_sra_i128(TCGv destl, TCGv desth,
TCGv src1l, TCGv src1h, TCGv shamt)
{
TCGv ls = tcg_temp_new();
TCGv rs = tcg_temp_new();
TCGv hs = tcg_temp_new();
TCGv ll = tcg_temp_new();
TCGv lr = tcg_temp_new();
TCGv h0 = tcg_temp_new();
TCGv h1 = tcg_temp_new();
TCGv zero = tcg_constant_tl(0);
tcg_gen_andi_tl(hs, shamt, 64);
tcg_gen_andi_tl(rs, shamt, 63);
tcg_gen_neg_tl(shamt, shamt);
tcg_gen_andi_tl(ls, shamt, 63);
tcg_gen_shr_tl(lr, src1l, rs);
tcg_gen_sar_tl(h1, src1h, rs);
tcg_gen_shl_tl(ll, src1h, ls);
tcg_gen_movcond_tl(TCG_COND_NE, ll, shamt, zero, ll, zero);
tcg_gen_or_tl(h0, ll, lr);
tcg_gen_sari_tl(lr, src1h, 63);
tcg_gen_movcond_tl(TCG_COND_NE, destl, hs, zero, h1, h0);
tcg_gen_movcond_tl(TCG_COND_NE, desth, hs, zero, lr, h1);
tcg_temp_free(ls);
tcg_temp_free(rs);
tcg_temp_free(hs);
tcg_temp_free(ll);
tcg_temp_free(lr);
tcg_temp_free(h0);
tcg_temp_free(h1);
}
static bool trans_sra(DisasContext *ctx, arg_sra *a)
{
return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl);
return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, gen_sra_i128);
}
static bool trans_xor(DisasContext *ctx, arg_xor *a)
@ -439,23 +584,44 @@ static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_64_OR_128BIT(ctx);
ctx->ol = MXL_RV32;
return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl, NULL);
}
static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_64_OR_128BIT(ctx);
ctx->ol = MXL_RV32;
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw);
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw, NULL);
}
static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_64_OR_128BIT(ctx);
ctx->ol = MXL_RV32;
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw);
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw, NULL);
}
static bool trans_sllid(DisasContext *ctx, arg_sllid *a)
{
REQUIRE_128BIT(ctx);
ctx->ol = MXL_RV64;
return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl, NULL);
}
static bool trans_srlid(DisasContext *ctx, arg_srlid *a)
{
REQUIRE_128BIT(ctx);
ctx->ol = MXL_RV64;
return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shri_tl, NULL);
}
static bool trans_sraid(DisasContext *ctx, arg_sraid *a)
{
REQUIRE_128BIT(ctx);
ctx->ol = MXL_RV64;
return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_sari_tl, NULL);
}
static bool trans_addw(DisasContext *ctx, arg_addw *a)
@ -474,25 +640,47 @@ static bool trans_subw(DisasContext *ctx, arg_subw *a)
static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_64_OR_128BIT(ctx);
ctx->ol = MXL_RV32;
return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl);
return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl, NULL);
}
static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_64_OR_128BIT(ctx);
ctx->ol = MXL_RV32;
return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl);
return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl, NULL);
}
static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_64_OR_128BIT(ctx);
ctx->ol = MXL_RV32;
return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl);
return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, NULL);
}
static bool trans_slld(DisasContext *ctx, arg_slld *a)
{
REQUIRE_128BIT(ctx);
ctx->ol = MXL_RV64;
return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl, NULL);
}
static bool trans_srld(DisasContext *ctx, arg_srld *a)
{
REQUIRE_128BIT(ctx);
ctx->ol = MXL_RV64;
return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl, NULL);
}
static bool trans_srad(DisasContext *ctx, arg_srad *a)
{
REQUIRE_128BIT(ctx);
ctx->ol = MXL_RV64;
return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, NULL);
}
static bool trans_fence(DisasContext *ctx, arg_fence *a)
{
/* FENCE is a full memory barrier. */