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target/i386: reimplement 0x0f 0xd0-0xd7, 0xe0-0xe7, 0xf0-0xf7, add AVX

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The more complicated ones here are d6-d7, e6-e7, f7.  The others
are trivial.

For LDDQU, using gen_load_sse directly might corrupt the register if
the second part of the load fails.  Therefore, add a custom X86_TYPE_WM
value; like X86_TYPE_W it does call gen_load(), but it also rejects a
value of 11 in the ModRM field like X86_TYPE_M.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2022-09-01 14:27:55 +02:00
parent ce4fcb9478
commit 6bbeb98d10
4 changed files with 122 additions and 11 deletions
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2
target/i386/tcg/translate.c
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@ -4783,7 +4783,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
#endif
if (use_new &&
((b >= 0x150 && b <= 0x17f) ||
(b >= 0x1d8 && b <= 0x1ff && (b & 8)))) {
(b >= 0x1d0 && b <= 0x1ff))) {
disas_insn_new(s, cpu, b + 0x100);
return s->pc;
}