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hw/sh4/r2d: Convert legacy qemu_allocate_irqs() to qemu_init_irqs()

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The FPGA exposes a fixed set of IRQs. Hold them in the FPGA
state and initialize them in place calling qemu_init_irqs().

Move r2d_fpga_irq enums earlier so we can use NR_IRQS within
the r2d_fpga_t structure. r2d_fpga_init() returns r2d_fpga_t,
and we dereference irq from it in r2d_init().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250121182445.35309-1-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2025-01-21 08:51:25 +01:00
parent d50280af1b
commit 6b8f40c61b
1 changed files with 21 additions and 17 deletions
Download patch file Download diff file Expand all files Collapse all files

38
hw/sh4/r2d.c
View file

@ -63,6 +63,12 @@
#define PA_VERREG 0x32 #define PA_VERREG 0x32
#define PA_OUTPORT 0x36 #define PA_OUTPORT 0x36
enum r2d_fpga_irq {
PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T,
SDCARD, PCI_INTA, PCI_INTB, EXT, TP,
NR_IRQS
};
typedef struct { typedef struct {
uint16_t bcr; uint16_t bcr;
uint16_t irlmsk; uint16_t irlmsk;
@ -88,15 +94,10 @@ typedef struct {
/* output pin */ /* output pin */
qemu_irq irl; qemu_irq irl;
IRQState irq[NR_IRQS];
MemoryRegion iomem; MemoryRegion iomem;
} r2d_fpga_t; } r2d_fpga_t;
enum r2d_fpga_irq {
PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T,
SDCARD, PCI_INTA, PCI_INTB, EXT, TP,
NR_IRQS
};
static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = { static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
[CF_IDE] = { 1, 1 << 9 }, [CF_IDE] = { 1, 1 << 9 },
[CF_CD] = { 2, 1 << 8 }, [CF_CD] = { 2, 1 << 8 },
@ -186,8 +187,8 @@ static const MemoryRegionOps r2d_fpga_ops = {
.endianness = DEVICE_NATIVE_ENDIAN, .endianness = DEVICE_NATIVE_ENDIAN,
}; };
static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem, static r2d_fpga_t *r2d_fpga_init(MemoryRegion *sysmem,
hwaddr base, qemu_irq irl) hwaddr base, qemu_irq irl)
{ {
r2d_fpga_t *s; r2d_fpga_t *s;
@ -197,7 +198,10 @@ static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem,
memory_region_init_io(&s->iomem, NULL, &r2d_fpga_ops, s, "r2d-fpga", 0x40); memory_region_init_io(&s->iomem, NULL, &r2d_fpga_ops, s, "r2d-fpga", 0x40);
memory_region_add_subregion(sysmem, base, &s->iomem); memory_region_add_subregion(sysmem, base, &s->iomem);
return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
qemu_init_irqs(s->irq, NR_IRQS, r2d_fpga_irq_set, s);
return s;
} }
typedef struct ResetData { typedef struct ResetData {
@ -239,13 +243,13 @@ static void r2d_init(MachineState *machine)
ResetData *reset_info; ResetData *reset_info;
struct SH7750State *s; struct SH7750State *s;
MemoryRegion *sdram = g_new(MemoryRegion, 1); MemoryRegion *sdram = g_new(MemoryRegion, 1);
qemu_irq *irq;
DriveInfo *dinfo; DriveInfo *dinfo;
DeviceState *dev; DeviceState *dev;
SysBusDevice *busdev; SysBusDevice *busdev;
MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *address_space_mem = get_system_memory();
PCIBus *pci_bus; PCIBus *pci_bus;
USBBus *usb_bus; USBBus *usb_bus;
r2d_fpga_t *fpga;
cpu = SUPERH_CPU(cpu_create(machine->cpu_type)); cpu = SUPERH_CPU(cpu_create(machine->cpu_type));
env = &cpu->env; env = &cpu->env;
@ -260,7 +264,7 @@ static void r2d_init(MachineState *machine)
memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram); memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram);
/* Register peripherals */ /* Register peripherals */
s = sh7750_init(cpu, address_space_mem); s = sh7750_init(cpu, address_space_mem);
irq = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s)); fpga = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s));
dev = qdev_new("sh_pci"); dev = qdev_new("sh_pci");
busdev = SYS_BUS_DEVICE(dev); busdev = SYS_BUS_DEVICE(dev);
@ -268,10 +272,10 @@ static void r2d_init(MachineState *machine)
pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci")); pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci"));
sysbus_mmio_map(busdev, 0, P4ADDR(0x1e200000)); sysbus_mmio_map(busdev, 0, P4ADDR(0x1e200000));
sysbus_mmio_map(busdev, 1, A7ADDR(0x1e200000)); sysbus_mmio_map(busdev, 1, A7ADDR(0x1e200000));
sysbus_connect_irq(busdev, 0, irq[PCI_INTA]); sysbus_connect_irq(busdev, 0, &fpga->irq[PCI_INTA]);
sysbus_connect_irq(busdev, 1, irq[PCI_INTB]); sysbus_connect_irq(busdev, 1, &fpga->irq[PCI_INTB]);
sysbus_connect_irq(busdev, 2, irq[PCI_INTC]); sysbus_connect_irq(busdev, 2, &fpga->irq[PCI_INTC]);
sysbus_connect_irq(busdev, 3, irq[PCI_INTD]); sysbus_connect_irq(busdev, 3, &fpga->irq[PCI_INTD]);
dev = qdev_new("sysbus-sm501"); dev = qdev_new("sysbus-sm501");
busdev = SYS_BUS_DEVICE(dev); busdev = SYS_BUS_DEVICE(dev);
@ -281,13 +285,13 @@ static void r2d_init(MachineState *machine)
sysbus_realize_and_unref(busdev, &error_fatal); sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0x10000000); sysbus_mmio_map(busdev, 0, 0x10000000);
sysbus_mmio_map(busdev, 1, 0x13e00000); sysbus_mmio_map(busdev, 1, 0x13e00000);
sysbus_connect_irq(busdev, 0, irq[SM501]); sysbus_connect_irq(busdev, 0, &fpga->irq[SM501]);
/* onboard CF (True IDE mode, Master only). */ /* onboard CF (True IDE mode, Master only). */
dinfo = drive_get(IF_IDE, 0, 0); dinfo = drive_get(IF_IDE, 0, 0);
dev = qdev_new("mmio-ide"); dev = qdev_new("mmio-ide");
busdev = SYS_BUS_DEVICE(dev); busdev = SYS_BUS_DEVICE(dev);
sysbus_connect_irq(busdev, 0, irq[CF_IDE]); sysbus_connect_irq(busdev, 0, &fpga->irq[CF_IDE]);
qdev_prop_set_uint32(dev, "shift", 1); qdev_prop_set_uint32(dev, "shift", 1);
sysbus_realize_and_unref(busdev, &error_fatal); sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0x14001000); sysbus_mmio_map(busdev, 0, 0x14001000);