mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-03 07:43:54 -06:00
* Various bug fixes
* Big cleanup of deprecated machines * Power11 support for spapr * XIVE improvements * Goodbye to Cedric and David as ppc reviewers, thank you both o7 -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEETkN92lZhb0MpsKeVZ7MCdqhiHK4FAmcoEicACgkQZ7MCdqhi HK5M8Q//fz+ZkJndXkBjb1Oinx+q+eVtNm2JrvcWIsXyhG3K+6VxYPp69H+SRv/Z TWuUqMQPxq8mhQvBJlDAttp/oaUEiOcCRvs/iUoBN12L4mVxXfdoT88TZ4frN3eP 8bePq+DW2N/7gpmsJm5CyEZPpcf9AjVHgLRp3KYFkOJ/14uzvuwnocU39gl+2IUh MXHTedQgMNXaKorJXk1NVdM6NxMuVhOvwxAs6ya2gwhxyA5tteo5PiQOnDJWkejf xg3RRsNzGYcs1Qg/3kFIf3RfEB0aYbPxROM8IfPaJWKN5KnMggj/JAkHyK1x/V3J wml7+cB0doMt/yRiuYJhXpyrtOqpvjRWPA6RhxECWW2kwrovv8NAF8IrFnw9NvOQ QC66ZaaFcbAcFrVT1e/iggU76d01II6m4OAgKcXw+FRHgps4VU9y83j7ApNnNUWN IXp9hkzoHi5VwX0FrG4ELUr2iEf1HASMvM8EZ/0AxzWj5iNtQB8lFsrEdaGVXyIS M5JaJeNjCn4koCyYaFSctH5eKtbzIwnGWnDcdTwaOuQ+9itBvY8O+HZalE6sAc5S kLFZ7i/Ut/qxbY5pMumt8LKD4pR1SsOxFB8dJCmn/f/tvRGtIVsoY6btNe4M0+24 42MxZbWO6W379C32bwbtsPiGA+aLSgShjP4cWm9cgRjz4RJFnwg= =vmIG -----END PGP SIGNATURE----- Merge tag 'pull-ppc-for-9.2-1-20241104' of https://gitlab.com/npiggin/qemu into staging * Various bug fixes * Big cleanup of deprecated machines * Power11 support for spapr * XIVE improvements * Goodbye to Cedric and David as ppc reviewers, thank you both o7 # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEETkN92lZhb0MpsKeVZ7MCdqhiHK4FAmcoEicACgkQZ7MCdqhi # HK5M8Q//fz+ZkJndXkBjb1Oinx+q+eVtNm2JrvcWIsXyhG3K+6VxYPp69H+SRv/Z # TWuUqMQPxq8mhQvBJlDAttp/oaUEiOcCRvs/iUoBN12L4mVxXfdoT88TZ4frN3eP # 8bePq+DW2N/7gpmsJm5CyEZPpcf9AjVHgLRp3KYFkOJ/14uzvuwnocU39gl+2IUh # MXHTedQgMNXaKorJXk1NVdM6NxMuVhOvwxAs6ya2gwhxyA5tteo5PiQOnDJWkejf # xg3RRsNzGYcs1Qg/3kFIf3RfEB0aYbPxROM8IfPaJWKN5KnMggj/JAkHyK1x/V3J # wml7+cB0doMt/yRiuYJhXpyrtOqpvjRWPA6RhxECWW2kwrovv8NAF8IrFnw9NvOQ # QC66ZaaFcbAcFrVT1e/iggU76d01II6m4OAgKcXw+FRHgps4VU9y83j7ApNnNUWN # IXp9hkzoHi5VwX0FrG4ELUr2iEf1HASMvM8EZ/0AxzWj5iNtQB8lFsrEdaGVXyIS # M5JaJeNjCn4koCyYaFSctH5eKtbzIwnGWnDcdTwaOuQ+9itBvY8O+HZalE6sAc5S # kLFZ7i/Ut/qxbY5pMumt8LKD4pR1SsOxFB8dJCmn/f/tvRGtIVsoY6btNe4M0+24 # 42MxZbWO6W379C32bwbtsPiGA+aLSgShjP4cWm9cgRjz4RJFnwg= # =vmIG # -----END PGP SIGNATURE----- # gpg: Signature made Mon 04 Nov 2024 00:15:35 GMT # gpg: using RSA key 4E437DDA56616F4329B0A79567B30276A8621CAE # gpg: Good signature from "Nicholas Piggin <npiggin@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 4E43 7DDA 5661 6F43 29B0 A795 67B3 0276 A862 1CAE * tag 'pull-ppc-for-9.2-1-20241104' of https://gitlab.com/npiggin/qemu: (67 commits) MAINTAINERS: Remove myself as reviewer MAINTAINERS: Remove myself from XIVE MAINTAINERS: Remove myself from the PowerNV machines hw/ppc: Consolidate ppc440 initial mapping creation functions hw/ppc: Consolidate e500 initial mapping creation functions tests/qtest: Add XIVE tests for the powernv10 machine pnv/xive2: TIMA CI ops using alternative offsets or byte lengths pnv/xive2: TIMA support for 8-byte OS context push for PHYP pnv/xive: Update PIPR when updating CPPR pnv/xive: Add special handling for pool targets ppc/xive2: Support "Pull Thread Context to Odd Thread Reporting Line" ppc/xive2: Change context/ring specific functions to be generic ppc/xive2: Support "Pull Thread Context to Register" operation ppc/xive2: Allow 1-byte write of Target field in TIMA ppc/xive2: Dump the VP-group and crowd tables with 'info pic' ppc/xive2: Dump more NVP state with 'info pic' pnv/xive2: Support for "OS LGS Push" TIMA operation ppc/xive2: Support TIMA "Pull OS Context to Odd Thread Reporting Line" pnv/xive2: Define OGEN field in the TIMA pnv/xive: TIMA patch sets pre-req alignment and formatting changes ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
6b829602e2
54 changed files with 1949 additions and 1228 deletions
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@ -824,13 +824,4 @@ extern const size_t hw_compat_2_5_len;
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extern GlobalProperty hw_compat_2_4[];
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extern const size_t hw_compat_2_4_len;
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extern GlobalProperty hw_compat_2_3[];
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extern const size_t hw_compat_2_3_len;
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extern GlobalProperty hw_compat_2_2[];
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extern const size_t hw_compat_2_2_len;
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extern GlobalProperty hw_compat_2_1[];
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extern const size_t hw_compat_2_1_len;
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#endif
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@ -53,7 +53,6 @@ struct SpaprPhbState {
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uint32_t index;
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uint64_t buid;
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char *dtbusname;
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bool dr_enabled;
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MemoryRegion memspace, iospace;
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hwaddr mem_win_addr, mem_win_size, mem64_win_addr, mem64_win_size;
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@ -84,10 +83,6 @@ struct SpaprPhbState {
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bool pcie_ecs; /* Allow access to PCIe extended config space? */
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/* Fields for migration compatibility hacks */
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bool pre_2_8_migration;
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uint32_t mig_liobn;
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hwaddr mig_mem_win_addr, mig_mem_win_size;
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hwaddr mig_io_win_addr, mig_io_win_size;
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bool pre_5_1_assoc;
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};
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@ -116,6 +116,13 @@ enum {
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#define PPC_SERIAL_MM_BAUDBASE 399193
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#ifndef CONFIG_USER_ONLY
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void booke206_set_tlb(ppcmas_tlb_t *tlb, target_ulong va, hwaddr pa,
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hwaddr len);
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void booke_set_tlb(ppcemb_tlb_t *tlb, target_ulong va, hwaddr pa,
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target_ulong size);
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#endif
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/* ppc_booke.c */
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void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags);
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#endif
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@ -141,11 +141,8 @@ struct SpaprMachineClass {
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MachineClass parent_class;
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/*< public >*/
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bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */
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bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */
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bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */
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bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */
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bool pre_2_10_has_unused_icps;
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bool legacy_irq_allocation;
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uint32_t nr_xirqs;
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bool broken_host_serial_model; /* present real host info to the guest */
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@ -28,7 +28,6 @@ struct SpaprCpuCore {
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/*< public >*/
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PowerPCCPU **threads;
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int node_id;
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bool pre_3_0_migration; /* older machine don't know about SpaprCpuState */
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};
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struct SpaprCpuCoreClass {
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@ -99,7 +99,8 @@
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#define GSB_VCPU_SPR_HASHKEYR 0x1050
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#define GSB_VCPU_SPR_HASHPKEYR 0x1051
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#define GSB_VCPU_SPR_CTRL 0x1052
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/* RESERVED 0x1053 - 0x1FFF */
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#define GSB_VCPU_SPR_DPDES 0x1053
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/* RESERVED 0x1054 - 0x1FFF */
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#define GSB_VCPU_SPR_CR 0x2000
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#define GSB_VCPU_SPR_PIDR 0x2001
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#define GSB_VCPU_SPR_DSISR 0x2002
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@ -210,11 +211,14 @@ typedef struct SpaprMachineStateNestedGuest {
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#define H_GUEST_CAPABILITIES_COPY_MEM 0x8000000000000000
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#define H_GUEST_CAPABILITIES_P9_MODE 0x4000000000000000
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#define H_GUEST_CAPABILITIES_P10_MODE 0x2000000000000000
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#define H_GUEST_CAP_VALID_MASK (H_GUEST_CAPABILITIES_P10_MODE | \
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#define H_GUEST_CAPABILITIES_P11_MODE 0x1000000000000000
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#define H_GUEST_CAP_VALID_MASK (H_GUEST_CAPABILITIES_P11_MODE | \
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H_GUEST_CAPABILITIES_P10_MODE | \
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H_GUEST_CAPABILITIES_P9_MODE)
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#define H_GUEST_CAP_COPY_MEM_BMAP 0
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#define H_GUEST_CAP_P9_MODE_BMAP 1
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#define H_GUEST_CAP_P10_MODE_BMAP 2
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#define H_GUEST_CAP_P11_MODE_BMAP 3
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#define PAPR_NESTED_GUEST_MAX 4096
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#define H_GUEST_DELETE_ALL_FLAG 0x8000000000000000ULL
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#define PAPR_NESTED_GUEST_VCPU_MAX 2048
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@ -218,7 +218,7 @@ static inline bool xive_source_esb_has_2page(XiveSource *xsrc)
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xsrc->esb_shift == XIVE_ESB_4K_2PAGE;
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}
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static inline size_t xive_source_esb_len(XiveSource *xsrc)
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static inline uint64_t xive_source_esb_len(XiveSource *xsrc)
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{
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return (1ull << xsrc->esb_shift) * xsrc->nr_irqs;
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}
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@ -533,7 +533,7 @@ Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp);
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void xive_tctx_reset(XiveTCTX *tctx);
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void xive_tctx_destroy(XiveTCTX *tctx);
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void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb);
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void xive_tctx_reset_os_signal(XiveTCTX *tctx);
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void xive_tctx_reset_signal(XiveTCTX *tctx, uint8_t ring);
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/*
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* KVM XIVE device helpers
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@ -53,6 +53,12 @@ typedef struct Xive2RouterClass {
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Xive2Nvp *nvp);
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int (*write_nvp)(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
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Xive2Nvp *nvp, uint8_t word_number);
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int (*get_nvgc)(Xive2Router *xrtr, bool crowd,
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uint8_t nvgc_blk, uint32_t nvgc_idx,
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Xive2Nvgc *nvgc);
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int (*write_nvgc)(Xive2Router *xrtr, bool crowd,
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uint8_t nvgc_blk, uint32_t nvgc_idx,
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Xive2Nvgc *nvgc);
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uint8_t (*get_block_id)(Xive2Router *xrtr);
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uint32_t (*get_config)(Xive2Router *xrtr);
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} Xive2RouterClass;
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@ -67,6 +73,12 @@ int xive2_router_get_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
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Xive2Nvp *nvp);
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int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
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Xive2Nvp *nvp, uint8_t word_number);
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int xive2_router_get_nvgc(Xive2Router *xrtr, bool crowd,
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uint8_t nvgc_blk, uint32_t nvgc_idx,
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Xive2Nvgc *nvgc);
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int xive2_router_write_nvgc(Xive2Router *xrtr, bool crowd,
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uint8_t nvgc_blk, uint32_t nvgc_idx,
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Xive2Nvgc *nvgc);
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uint32_t xive2_router_get_config(Xive2Router *xrtr);
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void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked);
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@ -107,5 +119,11 @@ void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
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uint64_t value, unsigned size);
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uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
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hwaddr offset, unsigned size);
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void xive2_tm_pull_os_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx,
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hwaddr offset, uint64_t value, unsigned size);
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void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTCTX *tctx,
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hwaddr offset, uint64_t value, unsigned size);
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void xive2_tm_pull_phys_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx,
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hwaddr offset, uint64_t value, unsigned size);
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#endif /* PPC_XIVE2_H */
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@ -19,16 +19,18 @@
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* mode (P10), the CAM line is slightly different as the VP space was
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* increased.
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*/
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#define TM2_QW0W2_VU PPC_BIT32(0)
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#define TM2_W2_VALID PPC_BIT32(0)
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#define TM2_W2_HW PPC_BIT32(1)
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#define TM2_QW0W2_VU TM2_W2_VALID
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#define TM2_QW0W2_LOGIC_SERV PPC_BITMASK32(4, 31)
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#define TM2_QW1W2_VO PPC_BIT32(0)
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#define TM2_QW1W2_HO PPC_BIT32(1)
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#define TM2_QW1W2_VO TM2_W2_VALID
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#define TM2_QW1W2_HO TM2_W2_HW
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#define TM2_QW1W2_OS_CAM PPC_BITMASK32(4, 31)
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#define TM2_QW2W2_VP PPC_BIT32(0)
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#define TM2_QW2W2_HP PPC_BIT32(1)
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#define TM2_QW2W2_VP TM2_W2_VALID
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#define TM2_QW2W2_HP TM2_W2_HW
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#define TM2_QW2W2_POOL_CAM PPC_BITMASK32(4, 31)
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#define TM2_QW3W2_VT PPC_BIT32(0)
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#define TM2_QW3W2_HT PPC_BIT32(1)
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#define TM2_QW3W2_VT TM2_W2_VALID
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#define TM2_QW3W2_HT TM2_W2_HW
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#define TM2_QW3W2_LP PPC_BIT32(6)
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#define TM2_QW3W2_LE PPC_BIT32(7)
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@ -151,6 +153,7 @@ typedef struct Xive2Nvp {
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#define NVP2_W0_VALID PPC_BIT32(0)
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#define NVP2_W0_HW PPC_BIT32(7)
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#define NVP2_W0_ESC_END PPC_BIT32(25) /* 'N' bit 0:ESB 1:END */
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#define NVP2_W0_PGOFIRST PPC_BITMASK32(26, 31)
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uint32_t w1;
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#define NVP2_W1_CO PPC_BIT32(13)
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#define NVP2_W1_CO_PRIV PPC_BITMASK32(14, 15)
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@ -171,7 +174,9 @@ typedef struct Xive2Nvp {
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#define NVP2_W5_VP_END_BLOCK PPC_BITMASK32(4, 7)
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#define NVP2_W5_VP_END_INDEX PPC_BITMASK32(8, 31)
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uint32_t w6;
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#define NVP2_W6_REPORTING_LINE PPC_BITMASK32(4, 31)
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uint32_t w7;
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#define NVP2_W7_REPORTING_LINE PPC_BITMASK32(0, 23)
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} Xive2Nvp;
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#define xive2_nvp_is_valid(nvp) (be32_to_cpu((nvp)->w0) & NVP2_W0_VALID)
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@ -209,6 +214,7 @@ void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx, GString *buf);
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typedef struct Xive2Nvgc {
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uint32_t w0;
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#define NVGC2_W0_VALID PPC_BIT32(0)
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#define NVGC2_W0_PGONEXT PPC_BITMASK32(26, 31)
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uint32_t w1;
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uint32_t w2;
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uint32_t w3;
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@ -218,4 +224,9 @@ typedef struct Xive2Nvgc {
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uint32_t w7;
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} Xive2Nvgc;
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#define xive2_nvgc_is_valid(nvgc) (be32_to_cpu((nvgc)->w0) & NVGC2_W0_VALID)
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void xive2_nvgc_pic_print_info(Xive2Nvgc *nvgc, uint32_t nvgc_idx,
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GString *buf);
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#endif /* PPC_XIVE2_REGS_H */
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@ -77,8 +77,11 @@
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#define TM_LSMFB 0x3 /* - + + + */
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#define TM_ACK_CNT 0x4 /* - + - - */
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#define TM_INC 0x5 /* - + - + */
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#define TM_LGS 0x5 /* + + + + */ /* Rename P10 */
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#define TM_AGE 0x6 /* - + - + */
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#define TM_T 0x6 /* - + - + */ /* Rename P10 */
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#define TM_PIPR 0x7 /* - + - + */
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#define TM_OGEN 0xF /* - + - - */ /* P10 only */
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#define TM_WORD0 0x0
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#define TM_WORD1 0x4
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@ -98,6 +101,7 @@
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#define TM_QW3W2_LP PPC_BIT32(6)
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#define TM_QW3W2_LE PPC_BIT32(7)
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#define TM_QW3W2_T PPC_BIT32(31)
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#define TM_QW3B8_VT PPC_BIT8(0)
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/*
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* In addition to normal loads to "peek" and writes (only when invalid)
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@ -114,23 +118,32 @@
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* Then we have all these "special" CI ops at these offset that trigger
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* all sorts of side effects:
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*/
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#define TM_SPC_ACK_EBB 0x800 /* Load8 ack EBB to reg*/
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#define TM_SPC_ACK_OS_REG 0x810 /* Load16 ack OS irq to reg */
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#define TM_SPC_ACK_EBB 0x800 /* Load8 ack EBB to reg */
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#define TM_SPC_ACK_OS_REG 0x810 /* Load16 ack OS irq to reg */
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#define TM_SPC_PUSH_USR_CTX 0x808 /* Store32 Push/Validate user context */
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#define TM_SPC_PULL_USR_CTX 0x808 /* Load32 Pull/Invalidate user
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* context */
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#define TM_SPC_SET_OS_PENDING 0x812 /* Store8 Set OS irq pending bit */
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#define TM_SPC_PULL_OS_CTX 0x818 /* Load32/Load64 Pull/Invalidate OS
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* context to reg */
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#define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate Pool
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* context to reg*/
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#define TM_SPC_ACK_HV_REG 0x830 /* Load16 ack HV irq to reg */
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#define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd
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* line */
|
||||
#define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line */
|
||||
#define TM_SPC_ACK_HV_POOL_EL 0xc20 /* Store8 ack HV evt pool to even
|
||||
* line */
|
||||
#define TM_SPC_ACK_HV_EL 0xc30 /* Store8 ack HV irq to even line */
|
||||
#define TM_SPC_PULL_USR_CTX 0x808 /* Load32 Pull/Invalidate user */
|
||||
/* context */
|
||||
#define TM_SPC_SET_OS_PENDING 0x812 /* Store8 Set OS irq pending bit */
|
||||
#define TM_SPC_PULL_OS_CTX_G2 0x810 /* Load32/Load64 Pull/Invalidate OS */
|
||||
/* context to reg */
|
||||
#define TM_SPC_PULL_OS_CTX 0x818 /* Load32/Load64 Pull/Invalidate OS */
|
||||
/* context to reg */
|
||||
#define TM_SPC_PULL_POOL_CTX_G2 0x820 /* Load32/Load64 Pull/Invalidate Pool */
|
||||
/* context to reg */
|
||||
#define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate Pool */
|
||||
/* context to reg */
|
||||
#define TM_SPC_ACK_HV_REG 0x830 /* Load16 ack HV irq to reg */
|
||||
#define TM_SPC_PULL_PHYS_CTX_G2 0x830 /* Load32 Pull phys ctx to reg */
|
||||
#define TM_SPC_PULL_PHYS_CTX 0x838 /* Load8 Pull phys ctx to reg */
|
||||
#define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd */
|
||||
/* line */
|
||||
#define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line */
|
||||
#define TM_SPC_PULL_OS_CTX_OL 0xc18 /* Pull/Invalidate OS context to */
|
||||
/* odd Thread reporting line */
|
||||
#define TM_SPC_ACK_HV_POOL_EL 0xc20 /* Store8 ack HV evt pool to even */
|
||||
/* line */
|
||||
#define TM_SPC_ACK_HV_EL 0xc30 /* Store8 ack HV irq to even line */
|
||||
#define TM_SPC_PULL_PHYS_CTX_OL 0xc38 /* Pull phys ctx to odd cache line */
|
||||
/* XXX more... */
|
||||
|
||||
/* NSR fields for the various QW ack types */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue