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target/avr: Improve decode of LDS, STS
The comment about not being able to define a field with zero bits is out of date since94597b6146
("decodetree: Allow !function with no input bits"). This fixes the missing load of imm in the disassembler. Cc: qemu-stable@nongnu.org Fixes:9d8caa67a2
("target/avr: Add support for disassembling via option '-d in_asm'") Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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1da8f3a3c5
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6b661b7ed7
2 changed files with 2 additions and 7 deletions
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@ -118,11 +118,8 @@ BRBC 1111 01 ....... ... @op_bit_imm
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@io_rd_imm .... . .. ..... .... &rd_imm rd=%rd imm=%io_imm
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@ldst_d .. . . .. . rd:5 . ... &rd_imm imm=%ldst_d_imm
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# The 16-bit immediate is completely in the next word.
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# Fields cannot be defined with no bits, so we cannot play
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# the same trick and append to a zero-bit value.
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# Defer reading the immediate until trans_{LDS,STS}.
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@ldst_s .... ... rd:5 .... imm=0
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%ldst_imm !function=next_word
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@ldst_s .... ... rd:5 .... imm=%ldst_imm
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MOV 0010 11 . ..... .... @op_rd_rr
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MOVW 0000 0001 .... .... &rd_rr rd=%rd_d rr=%rr_d
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@ -1578,7 +1578,6 @@ static bool trans_LDS(DisasContext *ctx, arg_LDS *a)
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TCGv Rd = cpu_r[a->rd];
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TCGv addr = tcg_temp_new_i32();
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TCGv H = cpu_rampD;
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a->imm = next_word(ctx);
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tcg_gen_mov_tl(addr, H); /* addr = H:M:L */
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tcg_gen_shli_tl(addr, addr, 16);
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@ -1783,7 +1782,6 @@ static bool trans_STS(DisasContext *ctx, arg_STS *a)
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TCGv Rd = cpu_r[a->rd];
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TCGv addr = tcg_temp_new_i32();
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TCGv H = cpu_rampD;
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a->imm = next_word(ctx);
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tcg_gen_mov_tl(addr, H); /* addr = H:M:L */
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tcg_gen_shli_tl(addr, addr, 16);
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