motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-06 01:03:55 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

ppc/pnv/phb4: Add pervasive chiplet support to PHB4/5

Browse source 
Each non-core chiplet on a chip has a "pervasive chiplet" unit and its
xscom register set. This adds support for PHB4/5.

skiboot reads the CPLT_CONF1 register in __phb4/5_get_max_link_width(),
which shows up as unimplemented xscom reads. Set a value in PCI CONF1
register's link-width field to demonstrate skiboot doing something
interesting with it.

In the bigger picture, it might be better to model the pervasive
chiplet type as parent that each non-core chiplet model derives from.
For now this is enough to get the PHB registers implemented and working
for skiboot, and provides a second example (after the N1 chiplet) that
will help if the design is reworked as such.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Nicholas Piggin 2024-11-16 20:19:19 +10:00
parent 7f98b4f25e
commit 6b56bb6dbc
4 changed files with 71 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

55
hw/pci-host/pnv_phb4_pec.c
View file

@ -197,6 +197,9 @@ static PnvPHB *pnv_pec_default_phb_realize(PnvPhb4PecState *pec,
return phb;
}
#define XPEC_P9_PCI_LANE_CFG PPC_BITMASK(10, 11)
#define XPEC_P10_PCI_LANE_CFG PPC_BITMASK(0, 1)
static void pnv_pec_realize(DeviceState *dev, Error **errp)
{
PnvPhb4PecState *pec = PNV_PHB4_PEC(dev);
@ -211,6 +214,43 @@ static void pnv_pec_realize(DeviceState *dev, Error **errp)
pec->num_phbs = pecc->num_phbs[pec->index];
/* Pervasive chiplet */
object_initialize_child(OBJECT(pec), "nest-pervasive-common",
&pec->nest_pervasive,
TYPE_PNV_NEST_CHIPLET_PERVASIVE);
if (!qdev_realize(DEVICE(&pec->nest_pervasive), NULL, errp)) {
return;
}
/* Set up pervasive chiplet registers */
/*
* Most registers are not set up, this just sets the PCI CONF1 link-width
* field because skiboot probes it.
*/
if (pecc->version == PNV_PHB4_VERSION) {
/*
* On P9, PEC2 has configurable 1/2/3-furcation).
* Make it trifurcated (x8, x4, x4) to match pnv_pec_num_phbs.
*/
if (pec->index == 2) {
pec->nest_pervasive.control_regs.cplt_cfg1 =
SETFIELD(XPEC_P9_PCI_LANE_CFG,
pec->nest_pervasive.control_regs.cplt_cfg1,
0b10);
}
} else if (pecc->version == PNV_PHB5_VERSION) {
/*
* On P10, both PECs are configurable 1/2/3-furcation).
* Both are trifurcated to match pnv_phb5_pec_num_stacks.
*/
pec->nest_pervasive.control_regs.cplt_cfg1 =
SETFIELD(XPEC_P10_PCI_LANE_CFG,
pec->nest_pervasive.control_regs.cplt_cfg1,
0b10);
} else {
g_assert_not_reached();
}
/* Create PHBs if running with defaults */
if (defaults_enabled()) {
g_assert(pec->num_phbs <= MAX_PHBS_PER_PEC);
@ -290,9 +330,16 @@ static const Property pnv_pec_properties[] = {
PnvChip *),
};
#define XPEC_PCI_CPLT_OFFSET 0x1000000ULL
static uint32_t pnv_pec_xscom_cplt_base(PnvPhb4PecState *pec)
{
return PNV9_XSCOM_PEC_NEST_CPLT_BASE + XPEC_PCI_CPLT_OFFSET * pec->index;
}
static uint32_t pnv_pec_xscom_pci_base(PnvPhb4PecState *pec)
{
return PNV9_XSCOM_PEC_PCI_BASE + 0x1000000 * pec->index;
return PNV9_XSCOM_PEC_PCI_BASE + XPEC_PCI_CPLT_OFFSET * pec->index;
}
static uint32_t pnv_pec_xscom_nest_base(PnvPhb4PecState *pec)
@ -321,6 +368,7 @@ static void pnv_pec_class_init(ObjectClass *klass, void *data)
device_class_set_props(dc, pnv_pec_properties);
dc->user_creatable = false;
pecc->xscom_cplt_base = pnv_pec_xscom_cplt_base;
pecc->xscom_nest_base = pnv_pec_xscom_nest_base;
pecc->xscom_pci_base = pnv_pec_xscom_pci_base;
pecc->xscom_nest_size = PNV9_XSCOM_PEC_NEST_SIZE;
@ -349,6 +397,10 @@ static const TypeInfo pnv_pec_type_info = {
/*
* POWER10 definitions
*/
static uint32_t pnv_phb5_pec_xscom_cplt_base(PnvPhb4PecState *pec)
{
return PNV10_XSCOM_PEC_NEST_CPLT_BASE + XPEC_PCI_CPLT_OFFSET * pec->index;
}
static uint32_t pnv_phb5_pec_xscom_pci_base(PnvPhb4PecState *pec)
{
@ -373,6 +425,7 @@ static void pnv_phb5_pec_class_init(ObjectClass *klass, void *data)
static const char compat[] = "ibm,power10-pbcq";
static const char stk_compat[] = "ibm,power10-phb-stack";
pecc->xscom_cplt_base = pnv_phb5_pec_xscom_cplt_base;
pecc->xscom_nest_base = pnv_phb5_pec_xscom_nest_base;
pecc->xscom_pci_base = pnv_phb5_pec_xscom_pci_base;
pecc->xscom_nest_size = PNV10_XSCOM_PEC_NEST_SIZE;