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tcg: Reset data_gen_ptr correctly
tcg/riscv: Implement host vector support tcg/ppc: Fix tcg_out_rlw_rc target/i386: Walk NPT in guest real mode target/i386: Use probe_access_full_mmu in ptw_translate linux-user: Fix build failure caused by missing __u64 on musl linux-user: Emulate /proc/self/maps under mmap_lock linux-user/riscv: Fix definition of RISCV_HWPROBE_EXT_ZVFHMIN linux-user/ppc: Fix sigmask endianness issue in sigreturn -----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmcYbccdHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV97TwgAmg27QFCdiTrqZgs2 P1AO40zTgyTAwWx2gykaEuDWNhz/uSWvlBRN0/636wqGPkbJtrRHYM26og4BAThh o172/IwiZqfKOR1ndHl9j3BrtmrlIlaEEjiikqy1MTZF127irV6JWoJE1mSUrAxy 3Cm1K4gnK/e1+LdWf4Lj+K2lE6PpAK/ppKggzOXhtEgKiH1l4bUCl/Fq54wqphUn YS+cpmgQDCkXFfmPbQqie0HDpe3bhb75qIDQrbC5JcZdHqV73rTwSZvfUOmS/5Re 18K6nfAXXT+Zm0IrJMey/7b1jUWF3nMUVCTuLvmhSOwBAkIvTVYHko9CjvLtM6YH UHu3yA== =V393 -----END PGP SIGNATURE----- Merge tag 'pull-tcg-20241022' of https://gitlab.com/rth7680/qemu into staging tcg: Reset data_gen_ptr correctly tcg/riscv: Implement host vector support tcg/ppc: Fix tcg_out_rlw_rc target/i386: Walk NPT in guest real mode target/i386: Use probe_access_full_mmu in ptw_translate linux-user: Fix build failure caused by missing __u64 on musl linux-user: Emulate /proc/self/maps under mmap_lock linux-user/riscv: Fix definition of RISCV_HWPROBE_EXT_ZVFHMIN linux-user/ppc: Fix sigmask endianness issue in sigreturn # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmcYbccdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV97TwgAmg27QFCdiTrqZgs2 # P1AO40zTgyTAwWx2gykaEuDWNhz/uSWvlBRN0/636wqGPkbJtrRHYM26og4BAThh # o172/IwiZqfKOR1ndHl9j3BrtmrlIlaEEjiikqy1MTZF127irV6JWoJE1mSUrAxy # 3Cm1K4gnK/e1+LdWf4Lj+K2lE6PpAK/ppKggzOXhtEgKiH1l4bUCl/Fq54wqphUn # YS+cpmgQDCkXFfmPbQqie0HDpe3bhb75qIDQrbC5JcZdHqV73rTwSZvfUOmS/5Re # 18K6nfAXXT+Zm0IrJMey/7b1jUWF3nMUVCTuLvmhSOwBAkIvTVYHko9CjvLtM6YH # UHu3yA== # =V393 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 23 Oct 2024 04:30:15 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20241022' of https://gitlab.com/rth7680/qemu: (24 commits) linux-user/riscv: Fix definition of RISCV_HWPROBE_EXT_ZVFHMIN linux-user: Fix build failure caused by missing __u64 on musl linux-user: Trace rt_sigprocmask's sigsets linux-user/ppc: Fix sigmask endianness issue in sigreturn linux-user: Emulate /proc/self/maps under mmap_lock target/i386: Remove ra parameter from ptw_translate target/i386: Use probe_access_full_mmu in ptw_translate target/i386: Walk NPT in guest real mode include/exec: Improve probe_access_full{, _mmu} documentation tcg/ppc: Fix tcg_out_rlw_rc tcg/riscv: Enable native vector support for TCG host tcg/riscv: Implement vector roti/v/x ops tcg/riscv: Implement vector shi/s/v ops tcg/riscv: Implement vector min/max ops tcg/riscv: Implement vector sat/mul ops tcg/riscv: Accept constant first argument to sub_vec tcg/riscv: Implement vector neg ops tcg/riscv: Implement vector cmp/cmpsel ops tcg/riscv: Add support for basic vector opcodes tcg/riscv: Implement vector mov/dup{m/i} ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
6b3756503b
19 changed files with 1152 additions and 175 deletions
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@ -628,7 +628,7 @@ static int do_setcontext(struct target_ucontext *ucp, CPUPPCState *env, int sig)
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if (!lock_user_struct(VERIFY_READ, mcp, mcp_addr, 1))
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return 1;
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target_to_host_sigset_internal(&blocked, &set);
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target_to_host_sigset(&blocked, &set);
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set_sigmask(&blocked);
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restore_user_regs(env, mcp, sig);
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@ -160,20 +160,21 @@ static const char * const target_signal_name[] = {
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#undef MAKE_SIG_ENTRY
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};
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static void
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print_signal_1(abi_ulong arg)
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{
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if (arg < ARRAY_SIZE(target_signal_name)) {
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qemu_log("%s", target_signal_name[arg]);
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} else {
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qemu_log(TARGET_ABI_FMT_lu, arg);
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}
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}
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static void
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print_signal(abi_ulong arg, int last)
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{
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const char *signal_name = NULL;
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if (arg < ARRAY_SIZE(target_signal_name)) {
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signal_name = target_signal_name[arg];
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}
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if (signal_name == NULL) {
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print_raw_param("%ld", arg, last);
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return;
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}
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qemu_log("%s%s", signal_name, get_comma(last));
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print_signal_1(arg);
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qemu_log("%s", get_comma(last));
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}
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static void print_si_code(int arg)
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@ -718,6 +719,51 @@ print_ipc(CPUArchState *cpu_env, const struct syscallname *name,
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}
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#endif
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#ifdef TARGET_NR_rt_sigprocmask
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static void print_target_sigset_t_1(target_sigset_t *set, int last)
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{
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bool first = true;
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int i, sig = 1;
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qemu_log("[");
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for (i = 0; i < TARGET_NSIG_WORDS; i++) {
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abi_ulong bits = 0;
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int j;
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__get_user(bits, &set->sig[i]);
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for (j = 0; j < sizeof(bits) * 8; j++) {
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if (bits & ((abi_ulong)1 << j)) {
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if (first) {
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first = false;
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} else {
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qemu_log(" ");
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}
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print_signal_1(sig);
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}
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sig++;
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}
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}
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qemu_log("]%s", get_comma(last));
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}
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static void print_target_sigset_t(abi_ulong addr, abi_ulong size, int last)
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{
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if (addr && size == sizeof(target_sigset_t)) {
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target_sigset_t *set;
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set = lock_user(VERIFY_READ, addr, sizeof(target_sigset_t), 1);
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if (set) {
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print_target_sigset_t_1(set, last);
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unlock_user(set, addr, 0);
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} else {
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print_pointer(addr, last);
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}
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} else {
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print_pointer(addr, last);
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}
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}
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#endif
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/*
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* Variants for the return value output function
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*/
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@ -3312,11 +3358,29 @@ print_rt_sigprocmask(CPUArchState *cpu_env, const struct syscallname *name,
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case TARGET_SIG_SETMASK: how = "SIG_SETMASK"; break;
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}
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qemu_log("%s,", how);
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print_pointer(arg1, 0);
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print_target_sigset_t(arg1, arg3, 0);
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print_pointer(arg2, 0);
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print_raw_param("%u", arg3, 1);
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print_syscall_epilogue(name);
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}
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static void
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print_rt_sigprocmask_ret(CPUArchState *cpu_env, const struct syscallname *name,
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abi_long ret, abi_long arg0, abi_long arg1,
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abi_long arg2, abi_long arg3, abi_long arg4,
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abi_long arg5)
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{
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if (!print_syscall_err(ret)) {
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qemu_log(TARGET_ABI_FMT_ld, ret);
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if (arg2) {
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qemu_log(" (oldset=");
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print_target_sigset_t(arg2, arg3, 1);
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qemu_log(")");
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}
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}
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qemu_log("\n");
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}
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#endif
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#ifdef TARGET_NR_rt_sigqueueinfo
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@ -1189,7 +1189,8 @@
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{ TARGET_NR_rt_sigpending, "rt_sigpending" , NULL, NULL, NULL },
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#endif
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#ifdef TARGET_NR_rt_sigprocmask
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{ TARGET_NR_rt_sigprocmask, "rt_sigprocmask" , NULL, print_rt_sigprocmask, NULL },
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{ TARGET_NR_rt_sigprocmask, "rt_sigprocmask" , NULL, print_rt_sigprocmask,
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print_rt_sigprocmask_ret },
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#endif
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#ifdef TARGET_NR_rt_sigqueueinfo
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{ TARGET_NR_rt_sigqueueinfo, "rt_sigqueueinfo" , NULL, print_rt_sigqueueinfo, NULL },
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@ -8150,17 +8150,19 @@ static int open_self_maps_1(CPUArchState *env, int fd, bool smaps)
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{
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struct open_self_maps_data d = {
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.ts = get_task_state(env_cpu(env)),
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.host_maps = read_self_maps(),
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.fd = fd,
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.smaps = smaps
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};
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mmap_lock();
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d.host_maps = read_self_maps();
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if (d.host_maps) {
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walk_memory_regions(&d, open_self_maps_2);
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free_self_maps(d.host_maps);
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} else {
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walk_memory_regions(&d, open_self_maps_3);
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}
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mmap_unlock();
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return 0;
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}
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@ -8942,7 +8944,7 @@ static int do_getdents64(abi_long dirfd, abi_long arg2, abi_long count)
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#define RISCV_HWPROBE_EXT_ZFHMIN (1 << 28)
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#define RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 29)
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#define RISCV_HWPROBE_EXT_ZVFH (1 << 30)
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#define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 31)
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#define RISCV_HWPROBE_EXT_ZVFHMIN (1ULL << 31)
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#define RISCV_HWPROBE_EXT_ZFA (1ULL << 32)
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#define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33)
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#define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34)
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@ -2750,9 +2750,9 @@ struct target_sched_param {
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/* from kernel's include/uapi/linux/openat2.h */
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struct open_how_ver0 {
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__u64 flags;
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__u64 mode;
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__u64 resolve;
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uint64_t flags;
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uint64_t mode;
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uint64_t resolve;
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};
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struct target_open_how_ver0 {
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abi_ullong flags;
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