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https://github.com/Motorhead1991/qemu.git
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Pull request
Farhan Ali's s390x host PCI support for the block/nvme.c driver. -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEhpWov9P5fNqsNXdanKSrs4Grc8gFAmgcviUACgkQnKSrs4Gr c8hRswgAupxH5Zhx50F7GzwZyu9TCF2sphEPd2VuFVxze8Sg6mXnJq5BFTjv9IuC 0trPppfDyKFKujDk+FA3pl9bT45btm0xctNbFYNRS3HXrVUyMQLy73MlFF2twa5g U3uiX2d7DAYOdi5O1Cn3bhlByDh4qSko7YyUDFKio+WU57cdJxEd+pUqwyVXrU3E AMC2ZmJdKFGGC+tWxBIAuWNc5apq9yzbiywR8z62/Z2IC+Bym0RpvCbdklqcZb8O tpGxDKN8bY6s+hy1NZmA8eBA/iCiu6SUFmNpoe2vSwCFEk9R3gi+UNcuTVt3FaWO lgzoZSOelmI3JkF0UBqvKsPXt3fdJw== =KII7 -----END PGP SIGNATURE----- Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging Pull request Farhan Ali's s390x host PCI support for the block/nvme.c driver. # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEhpWov9P5fNqsNXdanKSrs4Grc8gFAmgcviUACgkQnKSrs4Gr # c8hRswgAupxH5Zhx50F7GzwZyu9TCF2sphEPd2VuFVxze8Sg6mXnJq5BFTjv9IuC # 0trPppfDyKFKujDk+FA3pl9bT45btm0xctNbFYNRS3HXrVUyMQLy73MlFF2twa5g # U3uiX2d7DAYOdi5O1Cn3bhlByDh4qSko7YyUDFKio+WU57cdJxEd+pUqwyVXrU3E # AMC2ZmJdKFGGC+tWxBIAuWNc5apq9yzbiywR8z62/Z2IC+Bym0RpvCbdklqcZb8O # tpGxDKN8bY6s+hy1NZmA8eBA/iCiu6SUFmNpoe2vSwCFEk9R3gi+UNcuTVt3FaWO # lgzoZSOelmI3JkF0UBqvKsPXt3fdJw== # =KII7 # -----END PGP SIGNATURE----- # gpg: Signature made Thu 08 May 2025 10:22:29 EDT # gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [ultimate] # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [ultimate] # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * tag 'block-pull-request' of https://gitlab.com/stefanha/qemu: block/nvme: Use host PCI MMIO API include: Add a header to define host PCI MMIO functions util: Add functions for s390x mmio read/write Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
commit
6b18f6e342
5 changed files with 331 additions and 18 deletions
41
block/nvme.c
41
block/nvme.c
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@ -18,6 +18,7 @@
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#include "qobject/qstring.h"
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#include "qemu/defer-call.h"
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#include "qemu/error-report.h"
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#include "qemu/host-pci-mmio.h"
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#include "qemu/main-loop.h"
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#include "qemu/module.h"
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#include "qemu/cutils.h"
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@ -60,7 +61,7 @@ typedef struct {
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uint8_t *queue;
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uint64_t iova;
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/* Hardware MMIO register */
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volatile uint32_t *doorbell;
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uint32_t *doorbell;
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} NVMeQueue;
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typedef struct {
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@ -100,7 +101,7 @@ struct BDRVNVMeState {
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QEMUVFIOState *vfio;
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void *bar0_wo_map;
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/* Memory mapped registers */
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volatile struct {
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struct {
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uint32_t sq_tail;
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uint32_t cq_head;
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} *doorbells;
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@ -292,7 +293,7 @@ static void nvme_kick(NVMeQueuePair *q)
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assert(!(q->sq.tail & 0xFF00));
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/* Fence the write to submission queue entry before notifying the device. */
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smp_wmb();
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*q->sq.doorbell = cpu_to_le32(q->sq.tail);
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host_pci_stl_le_p(q->sq.doorbell, q->sq.tail);
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q->inflight += q->need_kick;
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q->need_kick = 0;
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}
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@ -441,7 +442,7 @@ static bool nvme_process_completion(NVMeQueuePair *q)
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if (progress) {
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/* Notify the device so it can post more completions. */
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smp_mb_release();
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*q->cq.doorbell = cpu_to_le32(q->cq.head);
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host_pci_stl_le_p(q->cq.doorbell, q->cq.head);
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nvme_wake_free_req_locked(q);
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}
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@ -460,7 +461,7 @@ static void nvme_process_completion_bh(void *opaque)
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* so notify the device that it has space to fill in more completions now.
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*/
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smp_mb_release();
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*q->cq.doorbell = cpu_to_le32(q->cq.head);
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host_pci_stl_le_p(q->cq.doorbell, q->cq.head);
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nvme_wake_free_req_locked(q);
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nvme_process_completion(q);
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@ -749,9 +750,10 @@ static int nvme_init(BlockDriverState *bs, const char *device, int namespace,
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int ret;
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uint64_t cap;
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uint32_t ver;
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uint32_t cc;
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uint64_t timeout_ms;
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uint64_t deadline, now;
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volatile NvmeBar *regs = NULL;
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NvmeBar *regs = NULL;
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qemu_co_mutex_init(&s->dma_map_lock);
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qemu_co_queue_init(&s->dma_flush_queue);
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@ -779,7 +781,7 @@ static int nvme_init(BlockDriverState *bs, const char *device, int namespace,
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/* Perform initialize sequence as described in NVMe spec "7.6.1
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* Initialization". */
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cap = le64_to_cpu(regs->cap);
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cap = host_pci_ldq_le_p(®s->cap);
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trace_nvme_controller_capability_raw(cap);
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trace_nvme_controller_capability("Maximum Queue Entries Supported",
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1 + NVME_CAP_MQES(cap));
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@ -805,16 +807,17 @@ static int nvme_init(BlockDriverState *bs, const char *device, int namespace,
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bs->bl.request_alignment = s->page_size;
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timeout_ms = MIN(500 * NVME_CAP_TO(cap), 30000);
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ver = le32_to_cpu(regs->vs);
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ver = host_pci_ldl_le_p(®s->vs);
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trace_nvme_controller_spec_version(extract32(ver, 16, 16),
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extract32(ver, 8, 8),
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extract32(ver, 0, 8));
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/* Reset device to get a clean state. */
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regs->cc = cpu_to_le32(le32_to_cpu(regs->cc) & 0xFE);
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cc = host_pci_ldl_le_p(®s->cc);
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host_pci_stl_le_p(®s->cc, cc & 0xFE);
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/* Wait for CSTS.RDY = 0. */
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deadline = qemu_clock_get_ns(QEMU_CLOCK_REALTIME) + timeout_ms * SCALE_MS;
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while (NVME_CSTS_RDY(le32_to_cpu(regs->csts))) {
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while (NVME_CSTS_RDY(host_pci_ldl_le_p(®s->csts))) {
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if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) {
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error_setg(errp, "Timeout while waiting for device to reset (%"
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PRId64 " ms)",
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@ -843,19 +846,21 @@ static int nvme_init(BlockDriverState *bs, const char *device, int namespace,
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s->queues[INDEX_ADMIN] = q;
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s->queue_count = 1;
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QEMU_BUILD_BUG_ON((NVME_QUEUE_SIZE - 1) & 0xF000);
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regs->aqa = cpu_to_le32(((NVME_QUEUE_SIZE - 1) << AQA_ACQS_SHIFT) |
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((NVME_QUEUE_SIZE - 1) << AQA_ASQS_SHIFT));
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regs->asq = cpu_to_le64(q->sq.iova);
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regs->acq = cpu_to_le64(q->cq.iova);
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host_pci_stl_le_p(®s->aqa,
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((NVME_QUEUE_SIZE - 1) << AQA_ACQS_SHIFT) |
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((NVME_QUEUE_SIZE - 1) << AQA_ASQS_SHIFT));
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host_pci_stq_le_p(®s->asq, q->sq.iova);
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host_pci_stq_le_p(®s->acq, q->cq.iova);
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/* After setting up all control registers we can enable device now. */
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regs->cc = cpu_to_le32((ctz32(NVME_CQ_ENTRY_BYTES) << CC_IOCQES_SHIFT) |
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(ctz32(NVME_SQ_ENTRY_BYTES) << CC_IOSQES_SHIFT) |
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CC_EN_MASK);
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host_pci_stl_le_p(®s->cc,
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(ctz32(NVME_CQ_ENTRY_BYTES) << CC_IOCQES_SHIFT) |
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(ctz32(NVME_SQ_ENTRY_BYTES) << CC_IOSQES_SHIFT) |
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CC_EN_MASK);
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/* Wait for CSTS.RDY = 1. */
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now = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
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deadline = now + timeout_ms * SCALE_MS;
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while (!NVME_CSTS_RDY(le32_to_cpu(regs->csts))) {
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while (!NVME_CSTS_RDY(host_pci_ldl_le_p(®s->csts))) {
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if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) {
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error_setg(errp, "Timeout while waiting for device to start (%"
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PRId64 " ms)",
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136
include/qemu/host-pci-mmio.h
Normal file
136
include/qemu/host-pci-mmio.h
Normal file
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@ -0,0 +1,136 @@
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/*
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* API for host PCI MMIO accesses (e.g. Linux VFIO BARs)
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*
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* Copyright 2025 IBM Corp.
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* Author(s): Farhan Ali <alifm@linux.ibm.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef HOST_PCI_MMIO_H
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#define HOST_PCI_MMIO_H
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#include "qemu/bswap.h"
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#include "qemu/s390x_pci_mmio.h"
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static inline uint8_t host_pci_ldub_p(const void *ioaddr)
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{
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uint8_t ret = 0;
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#ifdef __s390x__
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ret = s390x_pci_mmio_read_8(ioaddr);
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#else
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ret = ldub_p(ioaddr);
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#endif
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return ret;
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}
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static inline uint16_t host_pci_lduw_le_p(const void *ioaddr)
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{
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uint16_t ret = 0;
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#ifdef __s390x__
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ret = le16_to_cpu(s390x_pci_mmio_read_16(ioaddr));
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#else
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ret = lduw_le_p(ioaddr);
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#endif
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return ret;
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}
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static inline uint32_t host_pci_ldl_le_p(const void *ioaddr)
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{
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uint32_t ret = 0;
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#ifdef __s390x__
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ret = le32_to_cpu(s390x_pci_mmio_read_32(ioaddr));
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#else
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ret = ldl_le_p(ioaddr);
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#endif
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return ret;
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}
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static inline uint64_t host_pci_ldq_le_p(const void *ioaddr)
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{
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uint64_t ret = 0;
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#ifdef __s390x__
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ret = le64_to_cpu(s390x_pci_mmio_read_64(ioaddr));
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#else
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ret = ldq_le_p(ioaddr);
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#endif
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return ret;
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}
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static inline void host_pci_stb_p(void *ioaddr, uint8_t val)
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{
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#ifdef __s390x__
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s390x_pci_mmio_write_8(ioaddr, val);
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#else
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stb_p(ioaddr, val);
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#endif
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}
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static inline void host_pci_stw_le_p(void *ioaddr, uint16_t val)
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{
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#ifdef __s390x__
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s390x_pci_mmio_write_16(ioaddr, cpu_to_le16(val));
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#else
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stw_le_p(ioaddr, val);
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#endif
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}
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static inline void host_pci_stl_le_p(void *ioaddr, uint32_t val)
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{
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#ifdef __s390x__
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s390x_pci_mmio_write_32(ioaddr, cpu_to_le32(val));
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#else
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stl_le_p(ioaddr, val);
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#endif
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}
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static inline void host_pci_stq_le_p(void *ioaddr, uint64_t val)
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{
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#ifdef __s390x__
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s390x_pci_mmio_write_64(ioaddr, cpu_to_le64(val));
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#else
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stq_le_p(ioaddr, val);
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#endif
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}
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static inline uint64_t host_pci_ldn_le_p(const void *ioaddr, int sz)
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{
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switch (sz) {
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case 1:
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return host_pci_ldub_p(ioaddr);
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case 2:
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return host_pci_lduw_le_p(ioaddr);
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case 4:
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return host_pci_ldl_le_p(ioaddr);
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case 8:
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return host_pci_ldq_le_p(ioaddr);
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default:
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g_assert_not_reached();
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}
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}
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static inline void host_pci_stn_le_p(void *ioaddr, int sz, uint64_t v)
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{
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switch (sz) {
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case 1:
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host_pci_stb_p(ioaddr, v);
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break;
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case 2:
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host_pci_stw_le_p(ioaddr, v);
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break;
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case 4:
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host_pci_stl_le_p(ioaddr, v);
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break;
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case 8:
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host_pci_stq_le_p(ioaddr, v);
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break;
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default:
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g_assert_not_reached();
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}
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}
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#endif
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24
include/qemu/s390x_pci_mmio.h
Normal file
24
include/qemu/s390x_pci_mmio.h
Normal file
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@ -0,0 +1,24 @@
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/*
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* s390x PCI MMIO definitions
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*
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* Copyright 2025 IBM Corp.
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* Author(s): Farhan Ali <alifm@linux.ibm.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef S390X_PCI_MMIO_H
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#define S390X_PCI_MMIO_H
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#ifdef __s390x__
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uint8_t s390x_pci_mmio_read_8(const void *ioaddr);
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uint16_t s390x_pci_mmio_read_16(const void *ioaddr);
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uint32_t s390x_pci_mmio_read_32(const void *ioaddr);
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uint64_t s390x_pci_mmio_read_64(const void *ioaddr);
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void s390x_pci_mmio_write_8(void *ioaddr, uint8_t val);
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void s390x_pci_mmio_write_16(void *ioaddr, uint16_t val);
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void s390x_pci_mmio_write_32(void *ioaddr, uint32_t val);
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void s390x_pci_mmio_write_64(void *ioaddr, uint64_t val);
|
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#endif /* __s390x__ */
|
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|
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#endif /* S390X_PCI_MMIO_H */
|
||||
|
|
@ -133,4 +133,6 @@ elif cpu in ['ppc', 'ppc64']
|
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util_ss.add(files('cpuinfo-ppc.c'))
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elif cpu in ['riscv32', 'riscv64']
|
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util_ss.add(files('cpuinfo-riscv.c'))
|
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elif cpu == 's390x'
|
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util_ss.add(files('s390x_pci_mmio.c'))
|
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endif
|
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|
|
|
|||
146
util/s390x_pci_mmio.c
Normal file
146
util/s390x_pci_mmio.c
Normal file
|
|
@ -0,0 +1,146 @@
|
|||
/*
|
||||
* s390x PCI MMIO definitions
|
||||
*
|
||||
* Copyright 2025 IBM Corp.
|
||||
* Author(s): Farhan Ali <alifm@linux.ibm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
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#include <sys/syscall.h>
|
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#include "qemu/s390x_pci_mmio.h"
|
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#include "elf.h"
|
||||
|
||||
union register_pair {
|
||||
unsigned __int128 pair;
|
||||
struct {
|
||||
uint64_t even;
|
||||
uint64_t odd;
|
||||
};
|
||||
};
|
||||
|
||||
static bool is_mio_supported;
|
||||
|
||||
static __attribute__((constructor)) void check_is_mio_supported(void)
|
||||
{
|
||||
is_mio_supported = !!(qemu_getauxval(AT_HWCAP) & HWCAP_S390_PCI_MIO);
|
||||
}
|
||||
|
||||
static uint64_t s390x_pcilgi(const void *ioaddr, size_t len)
|
||||
{
|
||||
union register_pair ioaddr_len = { .even = (uint64_t)ioaddr,
|
||||
.odd = len };
|
||||
uint64_t val;
|
||||
int cc;
|
||||
|
||||
asm volatile(
|
||||
/* pcilgi */
|
||||
".insn rre,0xb9d60000,%[val],%[ioaddr_len]\n"
|
||||
"ipm %[cc]\n"
|
||||
"srl %[cc],28\n"
|
||||
: [cc] "=d"(cc), [val] "=d"(val),
|
||||
[ioaddr_len] "+d"(ioaddr_len.pair) :: "cc");
|
||||
|
||||
if (cc) {
|
||||
val = -1ULL;
|
||||
}
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
static void s390x_pcistgi(void *ioaddr, uint64_t val, size_t len)
|
||||
{
|
||||
union register_pair ioaddr_len = {.even = (uint64_t)ioaddr, .odd = len};
|
||||
|
||||
asm volatile (
|
||||
/* pcistgi */
|
||||
".insn rre,0xb9d40000,%[val],%[ioaddr_len]\n"
|
||||
: [ioaddr_len] "+d" (ioaddr_len.pair)
|
||||
: [val] "d" (val)
|
||||
: "cc", "memory");
|
||||
}
|
||||
|
||||
uint8_t s390x_pci_mmio_read_8(const void *ioaddr)
|
||||
{
|
||||
uint8_t val = 0;
|
||||
|
||||
if (is_mio_supported) {
|
||||
val = s390x_pcilgi(ioaddr, sizeof(val));
|
||||
} else {
|
||||
syscall(__NR_s390_pci_mmio_read, ioaddr, &val, sizeof(val));
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
uint16_t s390x_pci_mmio_read_16(const void *ioaddr)
|
||||
{
|
||||
uint16_t val = 0;
|
||||
|
||||
if (is_mio_supported) {
|
||||
val = s390x_pcilgi(ioaddr, sizeof(val));
|
||||
} else {
|
||||
syscall(__NR_s390_pci_mmio_read, ioaddr, &val, sizeof(val));
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
uint32_t s390x_pci_mmio_read_32(const void *ioaddr)
|
||||
{
|
||||
uint32_t val = 0;
|
||||
|
||||
if (is_mio_supported) {
|
||||
val = s390x_pcilgi(ioaddr, sizeof(val));
|
||||
} else {
|
||||
syscall(__NR_s390_pci_mmio_read, ioaddr, &val, sizeof(val));
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
uint64_t s390x_pci_mmio_read_64(const void *ioaddr)
|
||||
{
|
||||
uint64_t val = 0;
|
||||
|
||||
if (is_mio_supported) {
|
||||
val = s390x_pcilgi(ioaddr, sizeof(val));
|
||||
} else {
|
||||
syscall(__NR_s390_pci_mmio_read, ioaddr, &val, sizeof(val));
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
void s390x_pci_mmio_write_8(void *ioaddr, uint8_t val)
|
||||
{
|
||||
if (is_mio_supported) {
|
||||
s390x_pcistgi(ioaddr, val, sizeof(val));
|
||||
} else {
|
||||
syscall(__NR_s390_pci_mmio_write, ioaddr, &val, sizeof(val));
|
||||
}
|
||||
}
|
||||
|
||||
void s390x_pci_mmio_write_16(void *ioaddr, uint16_t val)
|
||||
{
|
||||
if (is_mio_supported) {
|
||||
s390x_pcistgi(ioaddr, val, sizeof(val));
|
||||
} else {
|
||||
syscall(__NR_s390_pci_mmio_write, ioaddr, &val, sizeof(val));
|
||||
}
|
||||
}
|
||||
|
||||
void s390x_pci_mmio_write_32(void *ioaddr, uint32_t val)
|
||||
{
|
||||
if (is_mio_supported) {
|
||||
s390x_pcistgi(ioaddr, val, sizeof(val));
|
||||
} else {
|
||||
syscall(__NR_s390_pci_mmio_write, ioaddr, &val, sizeof(val));
|
||||
}
|
||||
}
|
||||
|
||||
void s390x_pci_mmio_write_64(void *ioaddr, uint64_t val)
|
||||
{
|
||||
if (is_mio_supported) {
|
||||
s390x_pcistgi(ioaddr, val, sizeof(val));
|
||||
} else {
|
||||
syscall(__NR_s390_pci_mmio_write, ioaddr, &val, sizeof(val));
|
||||
}
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue