mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-10 02:54:58 -06:00
disas/libvixl: Update to libvixl 1.6
Update our copy of libvixl to upstream 1.6. There are no changes of any particular interest to QEMU, so this is simply keeping up with current upstream. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1412091418-25744-1-git-send-email-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
c6faa758e3
commit
6aea44fc2b
12 changed files with 718 additions and 335 deletions
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@ -57,7 +57,7 @@ char* Disassembler::GetOutput() {
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}
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void Disassembler::VisitAddSubImmediate(Instruction* instr) {
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void Disassembler::VisitAddSubImmediate(const Instruction* instr) {
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bool rd_is_zr = RdIsZROrSP(instr);
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bool stack_op = (rd_is_zr || RnIsZROrSP(instr)) &&
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(instr->ImmAddSub() == 0) ? true : false;
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@ -102,7 +102,7 @@ void Disassembler::VisitAddSubImmediate(Instruction* instr) {
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}
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void Disassembler::VisitAddSubShifted(Instruction* instr) {
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void Disassembler::VisitAddSubShifted(const Instruction* instr) {
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bool rd_is_zr = RdIsZROrSP(instr);
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bool rn_is_zr = RnIsZROrSP(instr);
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const char *mnemonic = "";
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@ -149,7 +149,7 @@ void Disassembler::VisitAddSubShifted(Instruction* instr) {
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}
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void Disassembler::VisitAddSubExtended(Instruction* instr) {
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void Disassembler::VisitAddSubExtended(const Instruction* instr) {
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bool rd_is_zr = RdIsZROrSP(instr);
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const char *mnemonic = "";
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Extend mode = static_cast<Extend>(instr->ExtendMode());
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@ -187,7 +187,7 @@ void Disassembler::VisitAddSubExtended(Instruction* instr) {
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}
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void Disassembler::VisitAddSubWithCarry(Instruction* instr) {
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void Disassembler::VisitAddSubWithCarry(const Instruction* instr) {
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bool rn_is_zr = RnIsZROrSP(instr);
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const char *mnemonic = "";
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const char *form = "'Rd, 'Rn, 'Rm";
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@ -222,7 +222,7 @@ void Disassembler::VisitAddSubWithCarry(Instruction* instr) {
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}
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void Disassembler::VisitLogicalImmediate(Instruction* instr) {
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void Disassembler::VisitLogicalImmediate(const Instruction* instr) {
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bool rd_is_zr = RdIsZROrSP(instr);
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bool rn_is_zr = RnIsZROrSP(instr);
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const char *mnemonic = "";
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@ -294,7 +294,7 @@ bool Disassembler::IsMovzMovnImm(unsigned reg_size, uint64_t value) {
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}
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void Disassembler::VisitLogicalShifted(Instruction* instr) {
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void Disassembler::VisitLogicalShifted(const Instruction* instr) {
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bool rd_is_zr = RdIsZROrSP(instr);
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bool rn_is_zr = RnIsZROrSP(instr);
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const char *mnemonic = "";
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@ -345,7 +345,7 @@ void Disassembler::VisitLogicalShifted(Instruction* instr) {
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}
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void Disassembler::VisitConditionalCompareRegister(Instruction* instr) {
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void Disassembler::VisitConditionalCompareRegister(const Instruction* instr) {
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const char *mnemonic = "";
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const char *form = "'Rn, 'Rm, 'INzcv, 'Cond";
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@ -360,7 +360,7 @@ void Disassembler::VisitConditionalCompareRegister(Instruction* instr) {
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}
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void Disassembler::VisitConditionalCompareImmediate(Instruction* instr) {
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void Disassembler::VisitConditionalCompareImmediate(const Instruction* instr) {
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const char *mnemonic = "";
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const char *form = "'Rn, 'IP, 'INzcv, 'Cond";
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@ -375,7 +375,7 @@ void Disassembler::VisitConditionalCompareImmediate(Instruction* instr) {
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}
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void Disassembler::VisitConditionalSelect(Instruction* instr) {
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void Disassembler::VisitConditionalSelect(const Instruction* instr) {
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bool rnm_is_zr = (RnIsZROrSP(instr) && RmIsZROrSP(instr));
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bool rn_is_rm = (instr->Rn() == instr->Rm());
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const char *mnemonic = "";
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@ -428,7 +428,7 @@ void Disassembler::VisitConditionalSelect(Instruction* instr) {
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}
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void Disassembler::VisitBitfield(Instruction* instr) {
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void Disassembler::VisitBitfield(const Instruction* instr) {
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unsigned s = instr->ImmS();
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unsigned r = instr->ImmR();
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unsigned rd_size_minus_1 =
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@ -506,7 +506,7 @@ void Disassembler::VisitBitfield(Instruction* instr) {
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}
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void Disassembler::VisitExtract(Instruction* instr) {
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void Disassembler::VisitExtract(const Instruction* instr) {
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const char *mnemonic = "";
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const char *form = "'Rd, 'Rn, 'Rm, 'IExtract";
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@ -527,7 +527,7 @@ void Disassembler::VisitExtract(Instruction* instr) {
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}
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void Disassembler::VisitPCRelAddressing(Instruction* instr) {
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void Disassembler::VisitPCRelAddressing(const Instruction* instr) {
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switch (instr->Mask(PCRelAddressingMask)) {
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case ADR: Format(instr, "adr", "'Xd, 'AddrPCRelByte"); break;
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case ADRP: Format(instr, "adrp", "'Xd, 'AddrPCRelPage"); break;
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@ -536,7 +536,7 @@ void Disassembler::VisitPCRelAddressing(Instruction* instr) {
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}
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void Disassembler::VisitConditionalBranch(Instruction* instr) {
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void Disassembler::VisitConditionalBranch(const Instruction* instr) {
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switch (instr->Mask(ConditionalBranchMask)) {
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case B_cond: Format(instr, "b.'CBrn", "'BImmCond"); break;
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default: VIXL_UNREACHABLE();
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@ -544,7 +544,8 @@ void Disassembler::VisitConditionalBranch(Instruction* instr) {
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}
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void Disassembler::VisitUnconditionalBranchToRegister(Instruction* instr) {
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void Disassembler::VisitUnconditionalBranchToRegister(
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const Instruction* instr) {
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const char *mnemonic = "unimplemented";
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const char *form = "'Xn";
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@ -564,7 +565,7 @@ void Disassembler::VisitUnconditionalBranchToRegister(Instruction* instr) {
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}
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void Disassembler::VisitUnconditionalBranch(Instruction* instr) {
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void Disassembler::VisitUnconditionalBranch(const Instruction* instr) {
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const char *mnemonic = "";
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const char *form = "'BImmUncn";
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@ -577,7 +578,7 @@ void Disassembler::VisitUnconditionalBranch(Instruction* instr) {
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}
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void Disassembler::VisitDataProcessing1Source(Instruction* instr) {
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void Disassembler::VisitDataProcessing1Source(const Instruction* instr) {
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const char *mnemonic = "";
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const char *form = "'Rd, 'Rn";
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@ -598,7 +599,7 @@ void Disassembler::VisitDataProcessing1Source(Instruction* instr) {
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}
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void Disassembler::VisitDataProcessing2Source(Instruction* instr) {
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void Disassembler::VisitDataProcessing2Source(const Instruction* instr) {
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const char *mnemonic = "unimplemented";
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const char *form = "'Rd, 'Rn, 'Rm";
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@ -619,7 +620,7 @@ void Disassembler::VisitDataProcessing2Source(Instruction* instr) {
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}
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void Disassembler::VisitDataProcessing3Source(Instruction* instr) {
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void Disassembler::VisitDataProcessing3Source(const Instruction* instr) {
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bool ra_is_zr = RaIsZROrSP(instr);
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const char *mnemonic = "";
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const char *form = "'Xd, 'Wn, 'Wm, 'Xa";
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@ -697,7 +698,7 @@ void Disassembler::VisitDataProcessing3Source(Instruction* instr) {
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}
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void Disassembler::VisitCompareBranch(Instruction* instr) {
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void Disassembler::VisitCompareBranch(const Instruction* instr) {
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const char *mnemonic = "";
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const char *form = "'Rt, 'BImmCmpa";
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@ -712,7 +713,7 @@ void Disassembler::VisitCompareBranch(Instruction* instr) {
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}
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void Disassembler::VisitTestBranch(Instruction* instr) {
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void Disassembler::VisitTestBranch(const Instruction* instr) {
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const char *mnemonic = "";
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// If the top bit of the immediate is clear, the tested register is
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// disassembled as Wt, otherwise Xt. As the top bit of the immediate is
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@ -729,7 +730,7 @@ void Disassembler::VisitTestBranch(Instruction* instr) {
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}
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void Disassembler::VisitMoveWideImmediate(Instruction* instr) {
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void Disassembler::VisitMoveWideImmediate(const Instruction* instr) {
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const char *mnemonic = "";
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const char *form = "'Rd, 'IMoveImm";
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@ -768,7 +769,7 @@ void Disassembler::VisitMoveWideImmediate(Instruction* instr) {
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V(LDR_s, "ldr", "'St") \
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V(LDR_d, "ldr", "'Dt")
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void Disassembler::VisitLoadStorePreIndex(Instruction* instr) {
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void Disassembler::VisitLoadStorePreIndex(const Instruction* instr) {
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const char *mnemonic = "unimplemented";
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const char *form = "(LoadStorePreIndex)";
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@ -782,7 +783,7 @@ void Disassembler::VisitLoadStorePreIndex(Instruction* instr) {
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}
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void Disassembler::VisitLoadStorePostIndex(Instruction* instr) {
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void Disassembler::VisitLoadStorePostIndex(const Instruction* instr) {
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const char *mnemonic = "unimplemented";
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const char *form = "(LoadStorePostIndex)";
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@ -796,7 +797,7 @@ void Disassembler::VisitLoadStorePostIndex(Instruction* instr) {
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}
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void Disassembler::VisitLoadStoreUnsignedOffset(Instruction* instr) {
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void Disassembler::VisitLoadStoreUnsignedOffset(const Instruction* instr) {
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const char *mnemonic = "unimplemented";
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const char *form = "(LoadStoreUnsignedOffset)";
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@ -811,7 +812,7 @@ void Disassembler::VisitLoadStoreUnsignedOffset(Instruction* instr) {
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}
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void Disassembler::VisitLoadStoreRegisterOffset(Instruction* instr) {
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void Disassembler::VisitLoadStoreRegisterOffset(const Instruction* instr) {
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const char *mnemonic = "unimplemented";
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const char *form = "(LoadStoreRegisterOffset)";
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@ -826,7 +827,7 @@ void Disassembler::VisitLoadStoreRegisterOffset(Instruction* instr) {
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}
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void Disassembler::VisitLoadStoreUnscaledOffset(Instruction* instr) {
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void Disassembler::VisitLoadStoreUnscaledOffset(const Instruction* instr) {
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const char *mnemonic = "unimplemented";
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const char *form = "'Wt, ['Xns'ILS]";
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const char *form_x = "'Xt, ['Xns'ILS]";
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@ -857,7 +858,7 @@ void Disassembler::VisitLoadStoreUnscaledOffset(Instruction* instr) {
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}
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void Disassembler::VisitLoadLiteral(Instruction* instr) {
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void Disassembler::VisitLoadLiteral(const Instruction* instr) {
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const char *mnemonic = "ldr";
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const char *form = "(LoadLiteral)";
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@ -866,6 +867,11 @@ void Disassembler::VisitLoadLiteral(Instruction* instr) {
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case LDR_x_lit: form = "'Xt, 'ILLiteral 'LValue"; break;
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case LDR_s_lit: form = "'St, 'ILLiteral 'LValue"; break;
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case LDR_d_lit: form = "'Dt, 'ILLiteral 'LValue"; break;
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case LDRSW_x_lit: {
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mnemonic = "ldrsw";
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form = "'Xt, 'ILLiteral 'LValue";
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break;
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}
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default: mnemonic = "unimplemented";
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}
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Format(instr, mnemonic, form);
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@ -883,7 +889,7 @@ void Disassembler::VisitLoadLiteral(Instruction* instr) {
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V(STP_d, "stp", "'Dt, 'Dt2", "8") \
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V(LDP_d, "ldp", "'Dt, 'Dt2", "8")
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void Disassembler::VisitLoadStorePairPostIndex(Instruction* instr) {
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void Disassembler::VisitLoadStorePairPostIndex(const Instruction* instr) {
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const char *mnemonic = "unimplemented";
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const char *form = "(LoadStorePairPostIndex)";
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@ -897,7 +903,7 @@ void Disassembler::VisitLoadStorePairPostIndex(Instruction* instr) {
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}
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void Disassembler::VisitLoadStorePairPreIndex(Instruction* instr) {
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void Disassembler::VisitLoadStorePairPreIndex(const Instruction* instr) {
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const char *mnemonic = "unimplemented";
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const char *form = "(LoadStorePairPreIndex)";
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@ -911,7 +917,7 @@ void Disassembler::VisitLoadStorePairPreIndex(Instruction* instr) {
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}
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void Disassembler::VisitLoadStorePairOffset(Instruction* instr) {
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void Disassembler::VisitLoadStorePairOffset(const Instruction* instr) {
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const char *mnemonic = "unimplemented";
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const char *form = "(LoadStorePairOffset)";
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@ -925,7 +931,7 @@ void Disassembler::VisitLoadStorePairOffset(Instruction* instr) {
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}
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void Disassembler::VisitLoadStorePairNonTemporal(Instruction* instr) {
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void Disassembler::VisitLoadStorePairNonTemporal(const Instruction* instr) {
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const char *mnemonic = "unimplemented";
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const char *form;
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@ -944,7 +950,7 @@ void Disassembler::VisitLoadStorePairNonTemporal(Instruction* instr) {
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}
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void Disassembler::VisitLoadStoreExclusive(Instruction* instr) {
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void Disassembler::VisitLoadStoreExclusive(const Instruction* instr) {
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const char *mnemonic = "unimplemented";
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const char *form;
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@ -987,7 +993,7 @@ void Disassembler::VisitLoadStoreExclusive(Instruction* instr) {
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}
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void Disassembler::VisitFPCompare(Instruction* instr) {
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void Disassembler::VisitFPCompare(const Instruction* instr) {
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const char *mnemonic = "unimplemented";
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const char *form = "'Fn, 'Fm";
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const char *form_zero = "'Fn, #0.0";
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@ -1003,7 +1009,7 @@ void Disassembler::VisitFPCompare(Instruction* instr) {
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}
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void Disassembler::VisitFPConditionalCompare(Instruction* instr) {
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void Disassembler::VisitFPConditionalCompare(const Instruction* instr) {
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const char *mnemonic = "unmplemented";
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const char *form = "'Fn, 'Fm, 'INzcv, 'Cond";
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@ -1018,7 +1024,7 @@ void Disassembler::VisitFPConditionalCompare(Instruction* instr) {
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}
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void Disassembler::VisitFPConditionalSelect(Instruction* instr) {
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void Disassembler::VisitFPConditionalSelect(const Instruction* instr) {
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const char *mnemonic = "";
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const char *form = "'Fd, 'Fn, 'Fm, 'Cond";
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@ -1031,7 +1037,7 @@ void Disassembler::VisitFPConditionalSelect(Instruction* instr) {
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}
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void Disassembler::VisitFPDataProcessing1Source(Instruction* instr) {
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void Disassembler::VisitFPDataProcessing1Source(const Instruction* instr) {
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const char *mnemonic = "unimplemented";
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const char *form = "'Fd, 'Fn";
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@ -1059,7 +1065,7 @@ void Disassembler::VisitFPDataProcessing1Source(Instruction* instr) {
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}
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void Disassembler::VisitFPDataProcessing2Source(Instruction* instr) {
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void Disassembler::VisitFPDataProcessing2Source(const Instruction* instr) {
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const char *mnemonic = "";
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const char *form = "'Fd, 'Fn, 'Fm";
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@ -1083,7 +1089,7 @@ void Disassembler::VisitFPDataProcessing2Source(Instruction* instr) {
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}
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void Disassembler::VisitFPDataProcessing3Source(Instruction* instr) {
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void Disassembler::VisitFPDataProcessing3Source(const Instruction* instr) {
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const char *mnemonic = "";
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const char *form = "'Fd, 'Fn, 'Fm, 'Fa";
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@ -1102,7 +1108,7 @@ void Disassembler::VisitFPDataProcessing3Source(Instruction* instr) {
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}
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void Disassembler::VisitFPImmediate(Instruction* instr) {
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void Disassembler::VisitFPImmediate(const Instruction* instr) {
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const char *mnemonic = "";
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const char *form = "(FPImmediate)";
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@ -1115,7 +1121,7 @@ void Disassembler::VisitFPImmediate(Instruction* instr) {
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}
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void Disassembler::VisitFPIntegerConvert(Instruction* instr) {
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void Disassembler::VisitFPIntegerConvert(const Instruction* instr) {
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const char *mnemonic = "unimplemented";
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const char *form = "(FPIntegerConvert)";
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const char *form_rf = "'Rd, 'Fn";
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@ -1171,7 +1177,7 @@ void Disassembler::VisitFPIntegerConvert(Instruction* instr) {
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}
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void Disassembler::VisitFPFixedPointConvert(Instruction* instr) {
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void Disassembler::VisitFPFixedPointConvert(const Instruction* instr) {
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const char *mnemonic = "";
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const char *form = "'Rd, 'Fn, 'IFPFBits";
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const char *form_fr = "'Fd, 'Rn, 'IFPFBits";
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@ -1199,7 +1205,7 @@ void Disassembler::VisitFPFixedPointConvert(Instruction* instr) {
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}
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void Disassembler::VisitSystem(Instruction* instr) {
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void Disassembler::VisitSystem(const Instruction* instr) {
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// Some system instructions hijack their Op and Cp fields to represent a
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// range of immediates instead of indicating a different instruction. This
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// makes the decoding tricky.
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@ -1267,7 +1273,7 @@ void Disassembler::VisitSystem(Instruction* instr) {
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}
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void Disassembler::VisitException(Instruction* instr) {
|
||||
void Disassembler::VisitException(const Instruction* instr) {
|
||||
const char *mnemonic = "unimplemented";
|
||||
const char *form = "'IDebug";
|
||||
|
||||
|
|
@ -1286,22 +1292,75 @@ void Disassembler::VisitException(Instruction* instr) {
|
|||
}
|
||||
|
||||
|
||||
void Disassembler::VisitUnimplemented(Instruction* instr) {
|
||||
void Disassembler::VisitUnimplemented(const Instruction* instr) {
|
||||
Format(instr, "unimplemented", "(Unimplemented)");
|
||||
}
|
||||
|
||||
|
||||
void Disassembler::VisitUnallocated(Instruction* instr) {
|
||||
void Disassembler::VisitUnallocated(const Instruction* instr) {
|
||||
Format(instr, "unallocated", "(Unallocated)");
|
||||
}
|
||||
|
||||
|
||||
void Disassembler::ProcessOutput(Instruction* /*instr*/) {
|
||||
void Disassembler::ProcessOutput(const Instruction* /*instr*/) {
|
||||
// The base disasm does nothing more than disassembling into a buffer.
|
||||
}
|
||||
|
||||
|
||||
void Disassembler::Format(Instruction* instr, const char* mnemonic,
|
||||
void Disassembler::AppendRegisterNameToOutput(const Instruction* instr,
|
||||
const CPURegister& reg) {
|
||||
USE(instr);
|
||||
VIXL_ASSERT(reg.IsValid());
|
||||
char reg_char;
|
||||
|
||||
if (reg.IsRegister()) {
|
||||
reg_char = reg.Is64Bits() ? 'x' : 'w';
|
||||
} else {
|
||||
VIXL_ASSERT(reg.IsFPRegister());
|
||||
reg_char = reg.Is64Bits() ? 'd' : 's';
|
||||
}
|
||||
|
||||
if (reg.IsFPRegister() || !(reg.Aliases(sp) || reg.Aliases(xzr))) {
|
||||
// A normal register: w0 - w30, x0 - x30, s0 - s31, d0 - d31.
|
||||
AppendToOutput("%c%d", reg_char, reg.code());
|
||||
} else if (reg.Aliases(sp)) {
|
||||
// Disassemble w31/x31 as stack pointer wsp/sp.
|
||||
AppendToOutput("%s", reg.Is64Bits() ? "sp" : "wsp");
|
||||
} else {
|
||||
// Disassemble w31/x31 as zero register wzr/xzr.
|
||||
AppendToOutput("%czr", reg_char);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void Disassembler::AppendPCRelativeOffsetToOutput(const Instruction* instr,
|
||||
int64_t offset) {
|
||||
USE(instr);
|
||||
char sign = (offset < 0) ? '-' : '+';
|
||||
AppendToOutput("#%c0x%" PRIx64, sign, std::abs(offset));
|
||||
}
|
||||
|
||||
|
||||
void Disassembler::AppendAddressToOutput(const Instruction* instr,
|
||||
const void* addr) {
|
||||
USE(instr);
|
||||
AppendToOutput("(addr %p)", addr);
|
||||
}
|
||||
|
||||
|
||||
void Disassembler::AppendCodeAddressToOutput(const Instruction* instr,
|
||||
const void* addr) {
|
||||
AppendAddressToOutput(instr, addr);
|
||||
}
|
||||
|
||||
|
||||
void Disassembler::AppendDataAddressToOutput(const Instruction* instr,
|
||||
const void* addr) {
|
||||
AppendAddressToOutput(instr, addr);
|
||||
}
|
||||
|
||||
|
||||
void Disassembler::Format(const Instruction* instr, const char* mnemonic,
|
||||
const char* format) {
|
||||
VIXL_ASSERT(mnemonic != NULL);
|
||||
ResetOutput();
|
||||
|
|
@ -1315,7 +1374,7 @@ void Disassembler::Format(Instruction* instr, const char* mnemonic,
|
|||
}
|
||||
|
||||
|
||||
void Disassembler::Substitute(Instruction* instr, const char* string) {
|
||||
void Disassembler::Substitute(const Instruction* instr, const char* string) {
|
||||
char chr = *string++;
|
||||
while (chr != '\0') {
|
||||
if (chr == '\'') {
|
||||
|
|
@ -1328,7 +1387,8 @@ void Disassembler::Substitute(Instruction* instr, const char* string) {
|
|||
}
|
||||
|
||||
|
||||
int Disassembler::SubstituteField(Instruction* instr, const char* format) {
|
||||
int Disassembler::SubstituteField(const Instruction* instr,
|
||||
const char* format) {
|
||||
switch (format[0]) {
|
||||
case 'R': // Register. X or W, selected by sf bit.
|
||||
case 'F': // FP Register. S or D, selected by type field.
|
||||
|
|
@ -1354,7 +1414,7 @@ int Disassembler::SubstituteField(Instruction* instr, const char* format) {
|
|||
}
|
||||
|
||||
|
||||
int Disassembler::SubstituteRegisterField(Instruction* instr,
|
||||
int Disassembler::SubstituteRegisterField(const Instruction* instr,
|
||||
const char* format) {
|
||||
unsigned reg_num = 0;
|
||||
unsigned field_len = 2;
|
||||
|
|
@ -1381,34 +1441,47 @@ int Disassembler::SubstituteRegisterField(Instruction* instr,
|
|||
field_len = 3;
|
||||
}
|
||||
|
||||
char reg_type;
|
||||
CPURegister::RegisterType reg_type;
|
||||
unsigned reg_size;
|
||||
|
||||
if (format[0] == 'R') {
|
||||
// Register type is R: use sf bit to choose X and W.
|
||||
reg_type = instr->SixtyFourBits() ? 'x' : 'w';
|
||||
reg_type = CPURegister::kRegister;
|
||||
reg_size = instr->SixtyFourBits() ? kXRegSize : kWRegSize;
|
||||
} else if (format[0] == 'F') {
|
||||
// Floating-point register: use type field to choose S or D.
|
||||
reg_type = ((instr->FPType() & 1) == 0) ? 's' : 'd';
|
||||
reg_type = CPURegister::kFPRegister;
|
||||
reg_size = ((instr->FPType() & 1) == 0) ? kSRegSize : kDRegSize;
|
||||
} else {
|
||||
// Register type is specified. Make it lower case.
|
||||
reg_type = format[0] + 0x20;
|
||||
// The register type is specified.
|
||||
switch (format[0]) {
|
||||
case 'W':
|
||||
reg_type = CPURegister::kRegister; reg_size = kWRegSize; break;
|
||||
case 'X':
|
||||
reg_type = CPURegister::kRegister; reg_size = kXRegSize; break;
|
||||
case 'S':
|
||||
reg_type = CPURegister::kFPRegister; reg_size = kSRegSize; break;
|
||||
case 'D':
|
||||
reg_type = CPURegister::kFPRegister; reg_size = kDRegSize; break;
|
||||
default:
|
||||
VIXL_UNREACHABLE();
|
||||
reg_type = CPURegister::kRegister;
|
||||
reg_size = kXRegSize;
|
||||
}
|
||||
}
|
||||
|
||||
if ((reg_num != kZeroRegCode) || (reg_type == 's') || (reg_type == 'd')) {
|
||||
// A normal register: w0 - w30, x0 - x30, s0 - s31, d0 - d31.
|
||||
AppendToOutput("%c%d", reg_type, reg_num);
|
||||
} else if (format[2] == 's') {
|
||||
// Disassemble w31/x31 as stack pointer wsp/sp.
|
||||
AppendToOutput("%s", (reg_type == 'w') ? "wsp" : "sp");
|
||||
} else {
|
||||
// Disassemble w31/x31 as zero register wzr/xzr.
|
||||
AppendToOutput("%czr", reg_type);
|
||||
if ((reg_type == CPURegister::kRegister) &&
|
||||
(reg_num == kZeroRegCode) && (format[2] == 's')) {
|
||||
reg_num = kSPRegInternalCode;
|
||||
}
|
||||
|
||||
AppendRegisterNameToOutput(instr, CPURegister(reg_num, reg_size, reg_type));
|
||||
|
||||
return field_len;
|
||||
}
|
||||
|
||||
|
||||
int Disassembler::SubstituteImmediateField(Instruction* instr,
|
||||
int Disassembler::SubstituteImmediateField(const Instruction* instr,
|
||||
const char* format) {
|
||||
VIXL_ASSERT(format[0] == 'I');
|
||||
|
||||
|
|
@ -1458,8 +1531,7 @@ int Disassembler::SubstituteImmediateField(Instruction* instr,
|
|||
}
|
||||
case 'C': { // ICondB - Immediate Conditional Branch.
|
||||
int64_t offset = instr->ImmCondBranch() << 2;
|
||||
char sign = (offset >= 0) ? '+' : '-';
|
||||
AppendToOutput("#%c0x%" PRIx64, sign, offset);
|
||||
AppendPCRelativeOffsetToOutput(instr, offset);
|
||||
return 6;
|
||||
}
|
||||
case 'A': { // IAddSub.
|
||||
|
|
@ -1522,7 +1594,7 @@ int Disassembler::SubstituteImmediateField(Instruction* instr,
|
|||
}
|
||||
|
||||
|
||||
int Disassembler::SubstituteBitfieldImmediateField(Instruction* instr,
|
||||
int Disassembler::SubstituteBitfieldImmediateField(const Instruction* instr,
|
||||
const char* format) {
|
||||
VIXL_ASSERT((format[0] == 'I') && (format[1] == 'B'));
|
||||
unsigned r = instr->ImmR();
|
||||
|
|
@ -1557,7 +1629,7 @@ int Disassembler::SubstituteBitfieldImmediateField(Instruction* instr,
|
|||
}
|
||||
|
||||
|
||||
int Disassembler::SubstituteLiteralField(Instruction* instr,
|
||||
int Disassembler::SubstituteLiteralField(const Instruction* instr,
|
||||
const char* format) {
|
||||
VIXL_ASSERT(strncmp(format, "LValue", 6) == 0);
|
||||
USE(format);
|
||||
|
|
@ -1565,16 +1637,21 @@ int Disassembler::SubstituteLiteralField(Instruction* instr,
|
|||
switch (instr->Mask(LoadLiteralMask)) {
|
||||
case LDR_w_lit:
|
||||
case LDR_x_lit:
|
||||
case LDRSW_x_lit:
|
||||
case LDR_s_lit:
|
||||
case LDR_d_lit: AppendToOutput("(addr %p)", instr->LiteralAddress()); break;
|
||||
default: VIXL_UNREACHABLE();
|
||||
case LDR_d_lit:
|
||||
AppendDataAddressToOutput(instr, instr->LiteralAddress());
|
||||
break;
|
||||
default:
|
||||
VIXL_UNREACHABLE();
|
||||
}
|
||||
|
||||
return 6;
|
||||
}
|
||||
|
||||
|
||||
int Disassembler::SubstituteShiftField(Instruction* instr, const char* format) {
|
||||
int Disassembler::SubstituteShiftField(const Instruction* instr,
|
||||
const char* format) {
|
||||
VIXL_ASSERT(format[0] == 'H');
|
||||
VIXL_ASSERT(instr->ShiftDP() <= 0x3);
|
||||
|
||||
|
|
@ -1597,7 +1674,7 @@ int Disassembler::SubstituteShiftField(Instruction* instr, const char* format) {
|
|||
}
|
||||
|
||||
|
||||
int Disassembler::SubstituteConditionField(Instruction* instr,
|
||||
int Disassembler::SubstituteConditionField(const Instruction* instr,
|
||||
const char* format) {
|
||||
VIXL_ASSERT(format[0] == 'C');
|
||||
const char* condition_code[] = { "eq", "ne", "hs", "lo",
|
||||
|
|
@ -1618,27 +1695,28 @@ int Disassembler::SubstituteConditionField(Instruction* instr,
|
|||
}
|
||||
|
||||
|
||||
int Disassembler::SubstitutePCRelAddressField(Instruction* instr,
|
||||
int Disassembler::SubstitutePCRelAddressField(const Instruction* instr,
|
||||
const char* format) {
|
||||
VIXL_ASSERT((strcmp(format, "AddrPCRelByte") == 0) || // Used by `adr`.
|
||||
(strcmp(format, "AddrPCRelPage") == 0)); // Used by `adrp`.
|
||||
|
||||
int64_t offset = instr->ImmPCRel();
|
||||
Instruction * base = instr;
|
||||
const Instruction * base = instr;
|
||||
|
||||
if (format[9] == 'P') {
|
||||
offset *= kPageSize;
|
||||
base = AlignDown(base, kPageSize);
|
||||
}
|
||||
|
||||
char sign = (offset < 0) ? '-' : '+';
|
||||
void * target = reinterpret_cast<void *>(base + offset);
|
||||
AppendToOutput("#%c0x%" PRIx64 " (addr %p)", sign, std::abs(offset), target);
|
||||
const void* target = reinterpret_cast<const void*>(base + offset);
|
||||
AppendPCRelativeOffsetToOutput(instr, offset);
|
||||
AppendToOutput(" ");
|
||||
AppendAddressToOutput(instr, target);
|
||||
return 13;
|
||||
}
|
||||
|
||||
|
||||
int Disassembler::SubstituteBranchTargetField(Instruction* instr,
|
||||
int Disassembler::SubstituteBranchTargetField(const Instruction* instr,
|
||||
const char* format) {
|
||||
VIXL_ASSERT(strncmp(format, "BImm", 4) == 0);
|
||||
|
||||
|
|
@ -1655,19 +1733,18 @@ int Disassembler::SubstituteBranchTargetField(Instruction* instr,
|
|||
default: VIXL_UNIMPLEMENTED();
|
||||
}
|
||||
offset <<= kInstructionSizeLog2;
|
||||
char sign = '+';
|
||||
if (offset < 0) {
|
||||
offset = -offset;
|
||||
sign = '-';
|
||||
}
|
||||
const void* target_address = reinterpret_cast<const void*>(instr + offset);
|
||||
VIXL_STATIC_ASSERT(sizeof(*instr) == 1);
|
||||
void * address = reinterpret_cast<void *>(instr + offset);
|
||||
AppendToOutput("#%c0x%" PRIx64 " (addr %p)", sign, offset, address);
|
||||
|
||||
AppendPCRelativeOffsetToOutput(instr, offset);
|
||||
AppendToOutput(" ");
|
||||
AppendCodeAddressToOutput(instr, target_address);
|
||||
|
||||
return 8;
|
||||
}
|
||||
|
||||
|
||||
int Disassembler::SubstituteExtendField(Instruction* instr,
|
||||
int Disassembler::SubstituteExtendField(const Instruction* instr,
|
||||
const char* format) {
|
||||
VIXL_ASSERT(strncmp(format, "Ext", 3) == 0);
|
||||
VIXL_ASSERT(instr->ExtendMode() <= 7);
|
||||
|
|
@ -1694,7 +1771,7 @@ int Disassembler::SubstituteExtendField(Instruction* instr,
|
|||
}
|
||||
|
||||
|
||||
int Disassembler::SubstituteLSRegOffsetField(Instruction* instr,
|
||||
int Disassembler::SubstituteLSRegOffsetField(const Instruction* instr,
|
||||
const char* format) {
|
||||
VIXL_ASSERT(strncmp(format, "Offsetreg", 9) == 0);
|
||||
const char* extend_mode[] = { "undefined", "undefined", "uxtw", "lsl",
|
||||
|
|
@ -1723,7 +1800,7 @@ int Disassembler::SubstituteLSRegOffsetField(Instruction* instr,
|
|||
}
|
||||
|
||||
|
||||
int Disassembler::SubstitutePrefetchField(Instruction* instr,
|
||||
int Disassembler::SubstitutePrefetchField(const Instruction* instr,
|
||||
const char* format) {
|
||||
VIXL_ASSERT(format[0] == 'P');
|
||||
USE(format);
|
||||
|
|
@ -1738,7 +1815,7 @@ int Disassembler::SubstitutePrefetchField(Instruction* instr,
|
|||
return 6;
|
||||
}
|
||||
|
||||
int Disassembler::SubstituteBarrierField(Instruction* instr,
|
||||
int Disassembler::SubstituteBarrierField(const Instruction* instr,
|
||||
const char* format) {
|
||||
VIXL_ASSERT(format[0] == 'M');
|
||||
USE(format);
|
||||
|
|
@ -1770,7 +1847,7 @@ void Disassembler::AppendToOutput(const char* format, ...) {
|
|||
}
|
||||
|
||||
|
||||
void PrintDisassembler::ProcessOutput(Instruction* instr) {
|
||||
void PrintDisassembler::ProcessOutput(const Instruction* instr) {
|
||||
fprintf(stream_, "0x%016" PRIx64 " %08" PRIx32 "\t\t%s\n",
|
||||
reinterpret_cast<uint64_t>(instr),
|
||||
instr->InstructionBits(),
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue