mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-04 00:03:54 -06:00
Remove Sun4c, Sun4d and a few CPUs
Sun4c and Sun4d architectures and related CPUs are not fully implemented (especially Sun4c MMU) and there has been no interest for them. Likewise, a few CPUs (Cypress, Ross etc) are only half implemented. Remove the machines and CPUs, they can be re-added if needed later. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl
parent
4f6ab397b6
commit
6a4e177114
6 changed files with 6 additions and 955 deletions
463
hw/sparc/sun4m.c
463
hw/sparc/sun4m.c
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@ -55,18 +55,6 @@
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* SPARCstation 20/xx, SPARCserver 20
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* SPARCstation 4
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*
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* Sun4d architecture was used in the following machines:
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*
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* SPARCcenter 2000
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* SPARCserver 1000
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*
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* Sun4c architecture was used in the following machines:
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* SPARCstation 1/1+, SPARCserver 1/1+
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* SPARCstation SLC
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* SPARCstation IPC
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* SPARCstation ELC
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* SPARCstation IPX
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*
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* See for example: http://www.sunhelp.org/faq/sunref1.html
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*/
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@ -104,36 +92,6 @@ struct sun4m_hwdef {
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uint8_t nvram_machine_id;
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};
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#define MAX_IOUNITS 5
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struct sun4d_hwdef {
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hwaddr iounit_bases[MAX_IOUNITS], slavio_base;
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hwaddr counter_base, nvram_base, ms_kb_base;
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hwaddr serial_base;
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hwaddr espdma_base, esp_base;
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hwaddr ledma_base, le_base;
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hwaddr tcx_base;
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hwaddr sbi_base;
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uint64_t max_mem;
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const char * const default_cpu_model;
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uint32_t iounit_version;
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uint16_t machine_id;
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uint8_t nvram_machine_id;
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};
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struct sun4c_hwdef {
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hwaddr iommu_base, slavio_base;
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hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
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hwaddr serial_base, fd_base;
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hwaddr idreg_base, dma_base, esp_base, le_base;
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hwaddr tcx_base, aux1_base;
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uint64_t max_mem;
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const char * const default_cpu_model;
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uint32_t iommu_version;
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uint16_t machine_id;
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uint8_t nvram_machine_id;
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};
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int DMA_get_channel_mode (int nchan)
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{
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return 0;
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@ -1052,7 +1010,6 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
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}
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enum {
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ss2_id = 0,
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ss5_id = 32,
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vger_id,
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lx_id,
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@ -1062,8 +1019,6 @@ enum {
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ss10_id = 64,
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ss20_id,
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ss600mp_id,
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ss1000_id = 96,
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ss2000_id,
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};
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static const struct sun4m_hwdef sun4m_hwdefs[] = {
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@ -1504,417 +1459,6 @@ static QEMUMachine sbook_machine = {
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DEFAULT_MACHINE_OPTIONS,
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};
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static const struct sun4d_hwdef sun4d_hwdefs[] = {
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/* SS-1000 */
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{
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.iounit_bases = {
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0xfe0200000ULL,
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0xfe1200000ULL,
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0xfe2200000ULL,
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0xfe3200000ULL,
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-1,
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},
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.tcx_base = 0x820000000ULL,
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.slavio_base = 0xf00000000ULL,
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.ms_kb_base = 0xf00240000ULL,
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.serial_base = 0xf00200000ULL,
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.nvram_base = 0xf00280000ULL,
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.counter_base = 0xf00300000ULL,
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.espdma_base = 0x800081000ULL,
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.esp_base = 0x800080000ULL,
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.ledma_base = 0x800040000ULL,
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.le_base = 0x800060000ULL,
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.sbi_base = 0xf02800000ULL,
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.nvram_machine_id = 0x80,
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.machine_id = ss1000_id,
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.iounit_version = 0x03000000,
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.max_mem = 0xf00000000ULL,
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.default_cpu_model = "TI SuperSparc II",
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},
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/* SS-2000 */
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{
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.iounit_bases = {
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0xfe0200000ULL,
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0xfe1200000ULL,
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0xfe2200000ULL,
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0xfe3200000ULL,
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0xfe4200000ULL,
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},
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.tcx_base = 0x820000000ULL,
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.slavio_base = 0xf00000000ULL,
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.ms_kb_base = 0xf00240000ULL,
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.serial_base = 0xf00200000ULL,
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.nvram_base = 0xf00280000ULL,
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.counter_base = 0xf00300000ULL,
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.espdma_base = 0x800081000ULL,
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.esp_base = 0x800080000ULL,
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.ledma_base = 0x800040000ULL,
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.le_base = 0x800060000ULL,
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.sbi_base = 0xf02800000ULL,
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.nvram_machine_id = 0x80,
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.machine_id = ss2000_id,
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.iounit_version = 0x03000000,
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.max_mem = 0xf00000000ULL,
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.default_cpu_model = "TI SuperSparc II",
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},
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};
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static DeviceState *sbi_init(hwaddr addr, qemu_irq **parent_irq)
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{
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DeviceState *dev;
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SysBusDevice *s;
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unsigned int i;
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dev = qdev_create(NULL, "sbi");
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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for (i = 0; i < MAX_CPUS; i++) {
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sysbus_connect_irq(s, i, *parent_irq[i]);
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}
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sysbus_mmio_map(s, 0, addr);
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return dev;
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}
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static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
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const char *boot_device,
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const char *kernel_filename,
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const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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unsigned int i;
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void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
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qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
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espdma_irq, ledma_irq;
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qemu_irq esp_reset, dma_enable;
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unsigned long kernel_size;
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void *fw_cfg;
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DeviceState *dev;
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/* init CPUs */
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if (!cpu_model)
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cpu_model = hwdef->default_cpu_model;
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for(i = 0; i < smp_cpus; i++) {
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cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
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}
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for (i = smp_cpus; i < MAX_CPUS; i++)
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cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
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/* set up devices */
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ram_init(0, RAM_size, hwdef->max_mem);
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prom_init(hwdef->slavio_base, bios_name);
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dev = sbi_init(hwdef->sbi_base, cpu_irqs);
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for (i = 0; i < 32; i++) {
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sbi_irq[i] = qdev_get_gpio_in(dev, i);
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}
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for (i = 0; i < MAX_CPUS; i++) {
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sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
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}
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for (i = 0; i < MAX_IOUNITS; i++)
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if (hwdef->iounit_bases[i] != (hwaddr)-1)
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iounits[i] = iommu_init(hwdef->iounit_bases[i],
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hwdef->iounit_version,
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sbi_irq[0]);
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espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
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iounits[0], &espdma_irq, 0);
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/* should be lebuffer instead */
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ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
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iounits[0], &ledma_irq, 0);
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if (graphic_depth != 8 && graphic_depth != 24) {
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fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
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exit (1);
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}
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tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
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graphic_depth);
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lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
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nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
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slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
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slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
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display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
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/* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
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Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
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escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
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serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
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if (drive_get_max_bus(IF_SCSI) > 0) {
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fprintf(stderr, "qemu: too many SCSI bus\n");
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exit(1);
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}
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esp_init(hwdef->esp_base, 2,
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espdma_memory_read, espdma_memory_write,
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espdma, espdma_irq, &esp_reset, &dma_enable);
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qdev_connect_gpio_out(espdma, 0, esp_reset);
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qdev_connect_gpio_out(espdma, 1, dma_enable);
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kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
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RAM_size);
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nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
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boot_device, RAM_size, kernel_size, graphic_width,
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graphic_height, graphic_depth, hwdef->nvram_machine_id,
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"Sun4d");
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fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
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fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
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fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
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fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
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fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
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fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
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fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
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fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
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if (kernel_cmdline) {
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fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
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pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
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fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
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} else {
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fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
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}
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fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
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fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
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fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
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qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
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}
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/* SPARCserver 1000 hardware initialisation */
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static void ss1000_init(QEMUMachineInitArgs *args)
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{
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ram_addr_t RAM_size = args->ram_size;
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const char *cpu_model = args->cpu_model;
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const char *kernel_filename = args->kernel_filename;
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const char *kernel_cmdline = args->kernel_cmdline;
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const char *initrd_filename = args->initrd_filename;
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const char *boot_device = args->boot_device;
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sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
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kernel_cmdline, initrd_filename, cpu_model);
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}
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/* SPARCcenter 2000 hardware initialisation */
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static void ss2000_init(QEMUMachineInitArgs *args)
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{
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ram_addr_t RAM_size = args->ram_size;
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const char *cpu_model = args->cpu_model;
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const char *kernel_filename = args->kernel_filename;
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const char *kernel_cmdline = args->kernel_cmdline;
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const char *initrd_filename = args->initrd_filename;
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const char *boot_device = args->boot_device;
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sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
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kernel_cmdline, initrd_filename, cpu_model);
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}
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static QEMUMachine ss1000_machine = {
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.name = "SS-1000",
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.desc = "Sun4d platform, SPARCserver 1000",
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.init = ss1000_init,
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.block_default_type = IF_SCSI,
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.max_cpus = 8,
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DEFAULT_MACHINE_OPTIONS,
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};
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static QEMUMachine ss2000_machine = {
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.name = "SS-2000",
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.desc = "Sun4d platform, SPARCcenter 2000",
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.init = ss2000_init,
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.block_default_type = IF_SCSI,
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.max_cpus = 20,
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DEFAULT_MACHINE_OPTIONS,
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};
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static const struct sun4c_hwdef sun4c_hwdefs[] = {
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/* SS-2 */
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{
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.iommu_base = 0xf8000000,
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.tcx_base = 0xfe000000,
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.slavio_base = 0xf6000000,
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.intctl_base = 0xf5000000,
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.counter_base = 0xf3000000,
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.ms_kb_base = 0xf0000000,
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.serial_base = 0xf1000000,
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.nvram_base = 0xf2000000,
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.fd_base = 0xf7200000,
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.dma_base = 0xf8400000,
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.esp_base = 0xf8800000,
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.le_base = 0xf8c00000,
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.aux1_base = 0xf7400003,
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.nvram_machine_id = 0x55,
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.machine_id = ss2_id,
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.max_mem = 0x10000000,
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.default_cpu_model = "Cypress CY7C601",
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},
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};
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static DeviceState *sun4c_intctl_init(hwaddr addr,
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qemu_irq *parent_irq)
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{
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DeviceState *dev;
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SysBusDevice *s;
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unsigned int i;
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dev = qdev_create(NULL, "sun4c_intctl");
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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for (i = 0; i < MAX_PILS; i++) {
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sysbus_connect_irq(s, i, parent_irq[i]);
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}
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sysbus_mmio_map(s, 0, addr);
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return dev;
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}
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static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
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const char *boot_device,
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const char *kernel_filename,
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const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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void *iommu, *espdma, *ledma, *nvram;
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qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
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qemu_irq esp_reset, dma_enable;
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qemu_irq fdc_tc;
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unsigned long kernel_size;
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DriveInfo *fd[MAX_FD];
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void *fw_cfg;
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DeviceState *dev;
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unsigned int i;
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/* init CPU */
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if (!cpu_model)
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cpu_model = hwdef->default_cpu_model;
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cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
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/* set up devices */
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ram_init(0, RAM_size, hwdef->max_mem);
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prom_init(hwdef->slavio_base, bios_name);
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dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
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for (i = 0; i < 8; i++) {
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slavio_irq[i] = qdev_get_gpio_in(dev, i);
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}
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iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
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slavio_irq[1]);
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espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
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iommu, &espdma_irq, 0);
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ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
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slavio_irq[3], iommu, &ledma_irq, 1);
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if (graphic_depth != 8 && graphic_depth != 24) {
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fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
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exit (1);
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}
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tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
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graphic_depth);
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lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
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nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
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slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
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display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
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/* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
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Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
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escc_init(hwdef->serial_base, slavio_irq[1],
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slavio_irq[1], serial_hds[0], serial_hds[1],
|
||||
ESCC_CLOCK, 1);
|
||||
|
||||
if (hwdef->fd_base != (hwaddr)-1) {
|
||||
/* there is zero or one floppy drive */
|
||||
memset(fd, 0, sizeof(fd));
|
||||
fd[0] = drive_get(IF_FLOPPY, 0, 0);
|
||||
sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
|
||||
&fdc_tc);
|
||||
} else {
|
||||
fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1);
|
||||
}
|
||||
|
||||
slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
|
||||
|
||||
if (drive_get_max_bus(IF_SCSI) > 0) {
|
||||
fprintf(stderr, "qemu: too many SCSI bus\n");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
esp_init(hwdef->esp_base, 2,
|
||||
espdma_memory_read, espdma_memory_write,
|
||||
espdma, espdma_irq, &esp_reset, &dma_enable);
|
||||
|
||||
qdev_connect_gpio_out(espdma, 0, esp_reset);
|
||||
qdev_connect_gpio_out(espdma, 1, dma_enable);
|
||||
|
||||
kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
|
||||
RAM_size);
|
||||
|
||||
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
||||
boot_device, RAM_size, kernel_size, graphic_width,
|
||||
graphic_height, graphic_depth, hwdef->nvram_machine_id,
|
||||
"Sun4c");
|
||||
|
||||
fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
|
||||
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
|
||||
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
||||
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
|
||||
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
|
||||
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
|
||||
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
|
||||
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
|
||||
if (kernel_cmdline) {
|
||||
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
|
||||
pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
|
||||
fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
|
||||
} else {
|
||||
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
||||
}
|
||||
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
|
||||
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
|
||||
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
||||
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
|
||||
}
|
||||
|
||||
/* SPARCstation 2 hardware initialisation */
|
||||
static void ss2_init(QEMUMachineInitArgs *args)
|
||||
{
|
||||
ram_addr_t RAM_size = args->ram_size;
|
||||
const char *cpu_model = args->cpu_model;
|
||||
const char *kernel_filename = args->kernel_filename;
|
||||
const char *kernel_cmdline = args->kernel_cmdline;
|
||||
const char *initrd_filename = args->initrd_filename;
|
||||
const char *boot_device = args->boot_device;
|
||||
sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
|
||||
kernel_cmdline, initrd_filename, cpu_model);
|
||||
}
|
||||
|
||||
static QEMUMachine ss2_machine = {
|
||||
.name = "SS-2",
|
||||
.desc = "Sun4c platform, SPARCstation 2",
|
||||
.init = ss2_init,
|
||||
.block_default_type = IF_SCSI,
|
||||
DEFAULT_MACHINE_OPTIONS,
|
||||
};
|
||||
|
||||
static void sun4m_register_types(void)
|
||||
{
|
||||
type_register_static(&idreg_info);
|
||||
|
|
@ -1923,7 +1467,7 @@ static void sun4m_register_types(void)
|
|||
type_register_static(&ram_info);
|
||||
}
|
||||
|
||||
static void ss2_machine_init(void)
|
||||
static void sun4m_machine_init(void)
|
||||
{
|
||||
qemu_register_machine(&ss5_machine);
|
||||
qemu_register_machine(&ss10_machine);
|
||||
|
|
@ -1934,10 +1478,7 @@ static void ss2_machine_init(void)
|
|||
qemu_register_machine(&ss4_machine);
|
||||
qemu_register_machine(&scls_machine);
|
||||
qemu_register_machine(&sbook_machine);
|
||||
qemu_register_machine(&ss1000_machine);
|
||||
qemu_register_machine(&ss2000_machine);
|
||||
qemu_register_machine(&ss2_machine);
|
||||
}
|
||||
|
||||
type_init(sun4m_register_types)
|
||||
machine_init(ss2_machine_init);
|
||||
machine_init(sun4m_machine_init);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue