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sparc32_dma: rename SPARC32_DMA type to SPARC32_DMA_DEVICE

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Also update the function names to match as appropriate. While we're
here rename the type from sparc32_dma to sparc32-dma in order to
match the current QOM convention.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Mark Cave-Ayland 2017-10-14 13:22:21 +01:00
parent 7fa00e2049
commit 6a1f53f0fe
2 changed files with 35 additions and 34 deletions
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67
hw/dma/sparc32_dma.c
View file

@ -61,12 +61,13 @@
/* XXX SCSI and ethernet should have different read-only bit masks */ /* XXX SCSI and ethernet should have different read-only bit masks */
#define DMA_CSR_RO_MASK 0xfe000007 #define DMA_CSR_RO_MASK 0xfe000007
#define TYPE_SPARC32_DMA "sparc32_dma" #define TYPE_SPARC32_DMA_DEVICE "sparc32-dma-device"
#define SPARC32_DMA(obj) OBJECT_CHECK(DMAState, (obj), TYPE_SPARC32_DMA) #define SPARC32_DMA_DEVICE(obj) OBJECT_CHECK(DMADeviceState, (obj), \
TYPE_SPARC32_DMA_DEVICE)
typedef struct DMAState DMAState; typedef struct DMADeviceState DMADeviceState;
struct DMAState { struct DMADeviceState {
SysBusDevice parent_obj; SysBusDevice parent_obj;
MemoryRegion iomem; MemoryRegion iomem;
@ -86,7 +87,7 @@ enum {
void ledma_memory_read(void *opaque, hwaddr addr, void ledma_memory_read(void *opaque, hwaddr addr,
uint8_t *buf, int len, int do_bswap) uint8_t *buf, int len, int do_bswap)
{ {
DMAState *s = opaque; DMADeviceState *s = opaque;
int i; int i;
addr |= s->dmaregs[3]; addr |= s->dmaregs[3];
@ -106,7 +107,7 @@ void ledma_memory_read(void *opaque, hwaddr addr,
void ledma_memory_write(void *opaque, hwaddr addr, void ledma_memory_write(void *opaque, hwaddr addr,
uint8_t *buf, int len, int do_bswap) uint8_t *buf, int len, int do_bswap)
{ {
DMAState *s = opaque; DMADeviceState *s = opaque;
int l, i; int l, i;
uint16_t tmp_buf[32]; uint16_t tmp_buf[32];
@ -134,7 +135,7 @@ void ledma_memory_write(void *opaque, hwaddr addr,
static void dma_set_irq(void *opaque, int irq, int level) static void dma_set_irq(void *opaque, int irq, int level)
{ {
DMAState *s = opaque; DMADeviceState *s = opaque;
if (level) { if (level) {
s->dmaregs[0] |= DMA_INTR; s->dmaregs[0] |= DMA_INTR;
if (s->dmaregs[0] & DMA_INTREN) { if (s->dmaregs[0] & DMA_INTREN) {
@ -154,7 +155,7 @@ static void dma_set_irq(void *opaque, int irq, int level)
void espdma_memory_read(void *opaque, uint8_t *buf, int len) void espdma_memory_read(void *opaque, uint8_t *buf, int len)
{ {
DMAState *s = opaque; DMADeviceState *s = opaque;
trace_espdma_memory_read(s->dmaregs[1]); trace_espdma_memory_read(s->dmaregs[1]);
sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len); sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len);
@ -163,7 +164,7 @@ void espdma_memory_read(void *opaque, uint8_t *buf, int len)
void espdma_memory_write(void *opaque, uint8_t *buf, int len) void espdma_memory_write(void *opaque, uint8_t *buf, int len)
{ {
DMAState *s = opaque; DMADeviceState *s = opaque;
trace_espdma_memory_write(s->dmaregs[1]); trace_espdma_memory_write(s->dmaregs[1]);
sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len); sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len);
@ -173,7 +174,7 @@ void espdma_memory_write(void *opaque, uint8_t *buf, int len)
static uint64_t dma_mem_read(void *opaque, hwaddr addr, static uint64_t dma_mem_read(void *opaque, hwaddr addr,
unsigned size) unsigned size)
{ {
DMAState *s = opaque; DMADeviceState *s = opaque;
uint32_t saddr; uint32_t saddr;
if (s->is_ledma && (addr > DMA_MAX_REG_OFFSET)) { if (s->is_ledma && (addr > DMA_MAX_REG_OFFSET)) {
@ -190,7 +191,7 @@ static uint64_t dma_mem_read(void *opaque, hwaddr addr,
static void dma_mem_write(void *opaque, hwaddr addr, static void dma_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size) uint64_t val, unsigned size)
{ {
DMAState *s = opaque; DMADeviceState *s = opaque;
uint32_t saddr; uint32_t saddr;
if (s->is_ledma && (addr > DMA_MAX_REG_OFFSET)) { if (s->is_ledma && (addr > DMA_MAX_REG_OFFSET)) {
@ -252,28 +253,28 @@ static const MemoryRegionOps dma_mem_ops = {
}, },
}; };
static void dma_reset(DeviceState *d) static void sparc32_dma_device_reset(DeviceState *d)
{ {
DMAState *s = SPARC32_DMA(d); DMADeviceState *s = SPARC32_DMA_DEVICE(d);
memset(s->dmaregs, 0, DMA_SIZE); memset(s->dmaregs, 0, DMA_SIZE);
s->dmaregs[0] = DMA_VER; s->dmaregs[0] = DMA_VER;
} }
static const VMStateDescription vmstate_dma = { static const VMStateDescription vmstate_sparc32_dma_device = {
.name ="sparc32_dma", .name ="sparc32_dma",
.version_id = 2, .version_id = 2,
.minimum_version_id = 2, .minimum_version_id = 2,
.fields = (VMStateField[]) { .fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(dmaregs, DMAState, DMA_REGS), VMSTATE_UINT32_ARRAY(dmaregs, DMADeviceState, DMA_REGS),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
} }
}; };
static void sparc32_dma_init(Object *obj) static void sparc32_dma_device_init(Object *obj)
{ {
DeviceState *dev = DEVICE(obj); DeviceState *dev = DEVICE(obj);
DMAState *s = SPARC32_DMA(obj); DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
sysbus_init_irq(sbd, &s->irq); sysbus_init_irq(sbd, &s->irq);
@ -284,9 +285,9 @@ static void sparc32_dma_init(Object *obj)
qdev_init_gpio_out(dev, s->gpio, 2); qdev_init_gpio_out(dev, s->gpio, 2);
} }
static void sparc32_dma_realize(DeviceState *dev, Error **errp) static void sparc32_dma_device_realize(DeviceState *dev, Error **errp)
{ {
DMAState *s = SPARC32_DMA(dev); DMADeviceState *s = SPARC32_DMA_DEVICE(dev);
int reg_size; int reg_size;
reg_size = s->is_ledma ? DMA_ETH_SIZE : DMA_SIZE; reg_size = s->is_ledma ? DMA_ETH_SIZE : DMA_SIZE;
@ -294,35 +295,35 @@ static void sparc32_dma_realize(DeviceState *dev, Error **errp)
"dma", reg_size); "dma", reg_size);
} }
static Property sparc32_dma_properties[] = { static Property sparc32_dma_device_properties[] = {
DEFINE_PROP_PTR("iommu_opaque", DMAState, iommu), DEFINE_PROP_PTR("iommu_opaque", DMADeviceState, iommu),
DEFINE_PROP_UINT32("is_ledma", DMAState, is_ledma, 0), DEFINE_PROP_UINT32("is_ledma", DMADeviceState, is_ledma, 0),
DEFINE_PROP_END_OF_LIST(), DEFINE_PROP_END_OF_LIST(),
}; };
static void sparc32_dma_class_init(ObjectClass *klass, void *data) static void sparc32_dma_device_class_init(ObjectClass *klass, void *data)
{ {
DeviceClass *dc = DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = dma_reset; dc->reset = sparc32_dma_device_reset;
dc->vmsd = &vmstate_dma; dc->vmsd = &vmstate_sparc32_dma_device;
dc->props = sparc32_dma_properties; dc->props = sparc32_dma_device_properties;
dc->realize = sparc32_dma_realize; dc->realize = sparc32_dma_device_realize;
/* Reason: pointer property "iommu_opaque" */ /* Reason: pointer property "iommu_opaque" */
dc->user_creatable = false; dc->user_creatable = false;
} }
static const TypeInfo sparc32_dma_info = { static const TypeInfo sparc32_dma_device_info = {
.name = TYPE_SPARC32_DMA, .name = TYPE_SPARC32_DMA_DEVICE,
.parent = TYPE_SYS_BUS_DEVICE, .parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(DMAState), .instance_size = sizeof(DMADeviceState),
.instance_init = sparc32_dma_init, .instance_init = sparc32_dma_device_init,
.class_init = sparc32_dma_class_init, .class_init = sparc32_dma_device_class_init,
}; };
static void sparc32_dma_register_types(void) static void sparc32_dma_register_types(void)
{ {
type_register_static(&sparc32_dma_info); type_register_static(&sparc32_dma_device_info);
} }
type_init(sparc32_dma_register_types) type_init(sparc32_dma_register_types)

2
hw/sparc/sun4m.c
View file

@ -312,7 +312,7 @@ static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq,
DeviceState *dev; DeviceState *dev;
SysBusDevice *s; SysBusDevice *s;
dev = qdev_create(NULL, "sparc32_dma"); dev = qdev_create(NULL, "sparc32-dma-device");
qdev_prop_set_ptr(dev, "iommu_opaque", iommu); qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
qdev_prop_set_uint32(dev, "is_ledma", is_ledma); qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
qdev_init_nofail(dev); qdev_init_nofail(dev);