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next-cube: move next_rtc_cmd_is_write() and next_rtc_data_in_irq() functions
Move these functions in next-cube.c so that they are with the rest of the next-rtc functions. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Thomas Huth <huth@tuxfamily.org> Message-ID: <20241222130012.1013374-32-mark.cave-ayland@ilande.co.uk> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
This commit is contained in:
Mark Cave-Ayland
Thomas Huth
parent
eb1f03642d
commit
6963b2c054
1 changed files with 86 additions and 86 deletions
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@ -175,92 +175,6 @@ static void next_scr2_led_update(NeXTPC *s)
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}
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}
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static bool next_rtc_cmd_is_write(uint8_t cmd)
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{
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return (cmd >= 0x80 && cmd <= 0x9f) ||
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(cmd == 0xb1);
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}
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static void next_rtc_data_in_irq(void *opaque, int n, int level)
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{
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NeXTRTC *rtc = NEXT_RTC(opaque);
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if (rtc->phase < 8) {
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rtc->command = (rtc->command << 1) | level;
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if (rtc->phase == 7 && !next_rtc_cmd_is_write(rtc->command)) {
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if (rtc->command <= 0x1f) {
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/* RAM registers */
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rtc->retval = rtc->ram[rtc->command];
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}
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if ((rtc->command >= 0x20) && (rtc->command <= 0x2f)) {
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/* RTC */
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time_t time_h = time(NULL);
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struct tm *info = localtime(&time_h);
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rtc->retval = 0;
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switch (rtc->command) {
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case 0x20:
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rtc->retval = SCR2_TOBCD(info->tm_sec);
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break;
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case 0x21:
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rtc->retval = SCR2_TOBCD(info->tm_min);
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break;
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case 0x22:
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rtc->retval = SCR2_TOBCD(info->tm_hour);
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break;
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case 0x24:
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rtc->retval = SCR2_TOBCD(info->tm_mday);
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break;
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case 0x25:
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rtc->retval = SCR2_TOBCD((info->tm_mon + 1));
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break;
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case 0x26:
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rtc->retval = SCR2_TOBCD((info->tm_year - 100));
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break;
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}
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}
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if (rtc->command == 0x30) {
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/* read the status 0x30 */
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rtc->retval = rtc->status;
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}
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if (rtc->command == 0x31) {
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/* read the control 0x31 */
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rtc->retval = rtc->control;
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}
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}
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}
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if (rtc->phase >= 8 && rtc->phase < 16) {
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if (next_rtc_cmd_is_write(rtc->command)) {
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/* Shift in value to write */
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rtc->value = (rtc->value << 1) | level;
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} else {
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/* Shift out value to read */
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if (rtc->retval & (0x80 >> (rtc->phase - 8))) {
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qemu_irq_raise(rtc->data_out_irq);
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} else {
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qemu_irq_lower(rtc->data_out_irq);
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}
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}
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}
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rtc->phase++;
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if (rtc->phase == 16 && next_rtc_cmd_is_write(rtc->command)) {
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if (rtc->command >= 0x80 && rtc->command <= 0x9f) {
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/* RAM registers */
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rtc->ram[rtc->command - 0x80] = rtc->value;
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}
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if (rtc->command == 0xb1) {
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/* write to 0x30 register */
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if (rtc->value & 0x04) {
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/* clear FTU */
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rtc->status = rtc->status & (~0x18);
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qemu_irq_lower(rtc->power_irq);
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}
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}
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}
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}
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static void next_scr2_rtc_update(NeXTPC *s)
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{
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uint8_t old_scr2, scr2_2;
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@ -1012,6 +926,92 @@ static const MemoryRegionOps next_dummy_en_ops = {
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static bool next_rtc_cmd_is_write(uint8_t cmd)
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{
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return (cmd >= 0x80 && cmd <= 0x9f) ||
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(cmd == 0xb1);
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}
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static void next_rtc_data_in_irq(void *opaque, int n, int level)
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{
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NeXTRTC *rtc = NEXT_RTC(opaque);
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if (rtc->phase < 8) {
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rtc->command = (rtc->command << 1) | level;
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if (rtc->phase == 7 && !next_rtc_cmd_is_write(rtc->command)) {
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if (rtc->command <= 0x1f) {
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/* RAM registers */
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rtc->retval = rtc->ram[rtc->command];
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}
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if ((rtc->command >= 0x20) && (rtc->command <= 0x2f)) {
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/* RTC */
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time_t time_h = time(NULL);
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struct tm *info = localtime(&time_h);
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rtc->retval = 0;
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switch (rtc->command) {
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case 0x20:
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rtc->retval = SCR2_TOBCD(info->tm_sec);
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break;
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case 0x21:
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rtc->retval = SCR2_TOBCD(info->tm_min);
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break;
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case 0x22:
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rtc->retval = SCR2_TOBCD(info->tm_hour);
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break;
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case 0x24:
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rtc->retval = SCR2_TOBCD(info->tm_mday);
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break;
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case 0x25:
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rtc->retval = SCR2_TOBCD((info->tm_mon + 1));
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break;
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case 0x26:
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rtc->retval = SCR2_TOBCD((info->tm_year - 100));
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break;
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}
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}
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if (rtc->command == 0x30) {
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/* read the status 0x30 */
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rtc->retval = rtc->status;
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}
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if (rtc->command == 0x31) {
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/* read the control 0x31 */
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rtc->retval = rtc->control;
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}
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}
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}
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if (rtc->phase >= 8 && rtc->phase < 16) {
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if (next_rtc_cmd_is_write(rtc->command)) {
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/* Shift in value to write */
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rtc->value = (rtc->value << 1) | level;
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} else {
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/* Shift out value to read */
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if (rtc->retval & (0x80 >> (rtc->phase - 8))) {
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qemu_irq_raise(rtc->data_out_irq);
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} else {
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qemu_irq_lower(rtc->data_out_irq);
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}
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}
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}
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rtc->phase++;
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if (rtc->phase == 16 && next_rtc_cmd_is_write(rtc->command)) {
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if (rtc->command >= 0x80 && rtc->command <= 0x9f) {
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/* RAM registers */
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rtc->ram[rtc->command - 0x80] = rtc->value;
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}
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if (rtc->command == 0xb1) {
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/* write to 0x30 register */
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if (rtc->value & 0x04) {
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/* clear FTU */
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rtc->status = rtc->status & (~0x18);
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qemu_irq_lower(rtc->power_irq);
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}
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}
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}
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}
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static void next_rtc_cmd_reset_irq(void *opaque, int n, int level)
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{
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NeXTRTC *rtc = NEXT_RTC(opaque);
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