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target-arm: c12_vbar -> vbar_el[]

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No functional change.
Preparation for adding EL2 and 3 versions of this reg.

Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1400980132-25949-9-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Edgar E. Iglesias 2014-05-27 17:09:51 +01:00 • committed by Peter Maydell
parent d81c519c40
commit 68fdb6c5b0
3 changed files with 5 additions and 5 deletions
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2
target-arm/cpu.h
View file

@ -198,7 +198,7 @@ typedef struct CPUARMState {
uint32_t c9_pmuserenr; /* perf monitor user enable */ uint32_t c9_pmuserenr; /* perf monitor user enable */
uint32_t c9_pminten; /* perf monitor interrupt enables */ uint32_t c9_pminten; /* perf monitor interrupt enables */
uint64_t mair_el1; uint64_t mair_el1;
uint64_t c12_vbar; /* vector base address register */ uint64_t vbar_el[2]; /* vector base address register */
uint32_t c13_fcse; /* FCSE PID. */ uint32_t c13_fcse; /* FCSE PID. */
uint64_t contextidr_el1; /* Context ID. */ uint64_t contextidr_el1; /* Context ID. */
uint64_t tpidr_el0; /* User RW Thread register. */ uint64_t tpidr_el0; /* User RW Thread register. */

2
target-arm/helper-a64.c
View file

@ -443,7 +443,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
{ {
ARMCPU *cpu = ARM_CPU(cs); ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env; CPUARMState *env = &cpu->env;
target_ulong addr = env->cp15.c12_vbar; target_ulong addr = env->cp15.vbar_el[1];
int i; int i;
if (arm_current_pl(env) == 0) { if (arm_current_pl(env) == 0) {

6
target-arm/helper.c
View file

@ -681,7 +681,7 @@ static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
* contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
* requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.) * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
*/ */
env->cp15.c12_vbar = value & ~0x1FULL; env->cp15.vbar_el[1] = value & ~0x1FULL;
} }
static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
@ -790,7 +790,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
{ .name = "VBAR", .state = ARM_CP_STATE_BOTH, { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .writefn = vbar_write, .access = PL1_RW, .writefn = vbar_write,
.fieldoffset = offsetof(CPUARMState, cp15.c12_vbar), .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]),
.resetvalue = 0 }, .resetvalue = 0 },
{ .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr), .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
@ -3403,7 +3403,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
* and is never in monitor mode this feature is always active. * and is never in monitor mode this feature is always active.
* Note: only bits 31:5 are valid. * Note: only bits 31:5 are valid.
*/ */
addr += env->cp15.c12_vbar; addr += env->cp15.vbar_el[1];
} }
switch_mode (env, new_mode); switch_mode (env, new_mode);
env->spsr = cpsr_read(env); env->spsr = cpsr_read(env);