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hw/nvram: Introduce Xilinx eFuse QOM

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This introduces the QOM for Xilinx eFuse, an one-time
field-programmable storage bit array.

The actual mmio interface to the array varies by device
families and will be provided in different change-sets.

Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
Message-id: 20210917052400.1249094-2-tong.ho@xilinx.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Tong Ho 2021-09-16 22:23:52 -07:00 • committed by Peter Maydell
parent 9fcd15b919
commit 68fbcc344e
5 changed files with 540 additions and 0 deletions
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7
hw/nvram/Kconfig
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@ -15,3 +15,10 @@ config NMC93XX_EEPROM
config CHRP_NVRAM
bool
config XLNX_EFUSE_CRC
bool
config XLNX_EFUSE
bool
select XLNX_EFUSE_CRC