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ahci: convert to memory API

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Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Avi Kivity 2011-08-08 16:09:14 +03:00 • committed by Anthony Liguori
parent da146d0aad
commit 67e576c262
3 changed files with 15 additions and 21 deletions
Download patch file Download diff file Expand all files Collapse all files

31
hw/ide/ahci.c
View file

@ -276,12 +276,12 @@ static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val)
} }
} }
static uint32_t ahci_mem_readl(void *ptr, target_phys_addr_t addr) static uint64_t ahci_mem_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{ {
AHCIState *s = ptr; AHCIState *s = opaque;
uint32_t val = 0; uint32_t val = 0;
addr = addr & 0xfff;
if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) {
switch (addr) { switch (addr) {
case HOST_CAP: case HOST_CAP:
@ -314,10 +314,10 @@ static uint32_t ahci_mem_readl(void *ptr, target_phys_addr_t addr)
static void ahci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val) static void ahci_mem_write(void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned size)
{ {
AHCIState *s = ptr; AHCIState *s = opaque;
addr = addr & 0xfff;
/* Only aligned reads are allowed on AHCI */ /* Only aligned reads are allowed on AHCI */
if (addr & 3) { if (addr & 3) {
@ -364,16 +364,10 @@ static void ahci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
} }
static CPUReadMemoryFunc * const ahci_readfn[3]={ static MemoryRegionOps ahci_mem_ops = {
ahci_mem_readl, .read = ahci_mem_read,
ahci_mem_readl, .write = ahci_mem_write,
ahci_mem_readl .endianness = DEVICE_LITTLE_ENDIAN,
};
static CPUWriteMemoryFunc * const ahci_writefn[3]={
ahci_mem_writel,
ahci_mem_writel,
ahci_mem_writel
}; };
static void ahci_reg_init(AHCIState *s) static void ahci_reg_init(AHCIState *s)
@ -1131,8 +1125,8 @@ void ahci_init(AHCIState *s, DeviceState *qdev, int ports)
s->ports = ports; s->ports = ports;
s->dev = qemu_mallocz(sizeof(AHCIDevice) * ports); s->dev = qemu_mallocz(sizeof(AHCIDevice) * ports);
ahci_reg_init(s); ahci_reg_init(s);
s->mem = cpu_register_io_memory(ahci_readfn, ahci_writefn, s, /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
DEVICE_LITTLE_ENDIAN); memory_region_init_io(&s->mem, &ahci_mem_ops, s, "ahci", 0x1000);
irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports); irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports);
for (i = 0; i < s->ports; i++) { for (i = 0; i < s->ports; i++) {
@ -1151,6 +1145,7 @@ void ahci_init(AHCIState *s, DeviceState *qdev, int ports)
void ahci_uninit(AHCIState *s) void ahci_uninit(AHCIState *s)
{ {
memory_region_destroy(&s->mem);
qemu_free(s->dev); qemu_free(s->dev);
} }

2
hw/ide/ahci.h
View file

@ -289,7 +289,7 @@ struct AHCIDevice {
typedef struct AHCIState { typedef struct AHCIState {
AHCIDevice *dev; AHCIDevice *dev;
AHCIControlRegs control_regs; AHCIControlRegs control_regs;
int mem; MemoryRegion mem;
int ports; int ports;
qemu_irq irq; qemu_irq irq;
} AHCIState; } AHCIState;

3
hw/ide/ich.c
View file

@ -98,8 +98,7 @@ static int pci_ich9_ahci_init(PCIDevice *dev)
msi_init(dev, 0x50, 1, true, false); msi_init(dev, 0x50, 1, true, false);
d->ahci.irq = d->card.irq[0]; d->ahci.irq = d->card.irq[0];
/* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */ pci_register_bar_region(&d->card, 5, 0, &d->ahci.mem);
pci_register_bar_simple(&d->card, 5, 0x1000, 0, d->ahci.mem);
return 0; return 0;
} }