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target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP
Implement the SADDLP, UADDLP, SADALP and UADALP instructions in the SIMD 2-reg misc category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-8-git-send-email-peter.maydell@linaro.org
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3 changed files with 139 additions and 1 deletions
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@ -293,3 +293,64 @@ float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, void *fpstp)
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}
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return float64_muladd(a, b, float64_three, float_muladd_halve_result, fpst);
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}
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/* Pairwise long add: add pairs of adjacent elements into
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* double-width elements in the result (eg _s8 is an 8x8->16 op)
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*/
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uint64_t HELPER(neon_addlp_s8)(uint64_t a)
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{
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uint64_t nsignmask = 0x0080008000800080ULL;
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uint64_t wsignmask = 0x8000800080008000ULL;
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uint64_t elementmask = 0x00ff00ff00ff00ffULL;
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uint64_t tmp1, tmp2;
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uint64_t res, signres;
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/* Extract odd elements, sign extend each to a 16 bit field */
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tmp1 = a & elementmask;
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tmp1 ^= nsignmask;
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tmp1 |= wsignmask;
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tmp1 = (tmp1 - nsignmask) ^ wsignmask;
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/* Ditto for the even elements */
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tmp2 = (a >> 8) & elementmask;
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tmp2 ^= nsignmask;
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tmp2 |= wsignmask;
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tmp2 = (tmp2 - nsignmask) ^ wsignmask;
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/* calculate the result by summing bits 0..14, 16..22, etc,
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* and then adjusting the sign bits 15, 23, etc manually.
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* This ensures the addition can't overflow the 16 bit field.
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*/
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signres = (tmp1 ^ tmp2) & wsignmask;
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res = (tmp1 & ~wsignmask) + (tmp2 & ~wsignmask);
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res ^= signres;
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return res;
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}
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uint64_t HELPER(neon_addlp_u8)(uint64_t a)
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{
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uint64_t tmp;
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tmp = a & 0x00ff00ff00ff00ffULL;
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tmp += (a >> 8) & 0x00ff00ff00ff00ffULL;
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return tmp;
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}
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uint64_t HELPER(neon_addlp_s16)(uint64_t a)
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{
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int32_t reslo, reshi;
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reslo = (int32_t)(int16_t)a + (int32_t)(int16_t)(a >> 16);
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reshi = (int32_t)(int16_t)(a >> 32) + (int32_t)(int16_t)(a >> 48);
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return (uint32_t)reslo | (((uint64_t)reshi) << 32);
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}
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uint64_t HELPER(neon_addlp_u16)(uint64_t a)
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{
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uint64_t tmp;
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tmp = a & 0x0000ffff0000ffffULL;
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tmp += (a >> 16) & 0x0000ffff0000ffffULL;
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return tmp;
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}
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