arm: spelling fixes

Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Michael Tokarev 2023-07-14 14:14:49 +03:00
parent cced0d6539
commit 673d821541
24 changed files with 30 additions and 30 deletions

View file

@ -1,6 +1,6 @@
from __future__ import print_function
#
# Test the SVE registers are visable and changeable via gdbstub
# Test the SVE registers are visible and changeable via gdbstub
#
# This is launched via tests/guest-debug/run-test.py
#

View file

@ -28,7 +28,7 @@ asm(
" fmopa za1.s, p0/m, p0/m, z0.s, z0.s\n"
/*
* Read the first 4x4 sub-matrix of elements from tile 1:
* Note that za1h should be interchangable here.
* Note that za1h should be interchangeable here.
*/
" mov w12, #0\n"
" mova z0.s, p0/m, za1v.s[w12, #0]\n"

View file

@ -9,7 +9,7 @@
/*
* Semihosting interface on ARM AArch64
* See "Semihosting for AArch32 and AArch64 Relase 2.0" by ARM
* See "Semihosting for AArch32 and AArch64 Release 2.0" by ARM
* w0 - semihosting call number
* x1 - semihosting parameter
*/
@ -147,7 +147,7 @@ __start:
* T0SZ[5:0] = 2^(64 - 25)
*
* The size of T0SZ controls what the initial lookup level. It
* would be nice to start at level 2 but unfortunatly for a
* would be nice to start at level 2 but unfortunately for a
* flat-mapping on the virt machine we need to handle IA's
* with at least 1gb range to see RAM. So we start with a
* level 1 lookup.
@ -189,7 +189,7 @@ __start:
msr cpacr_el1, x0
/* Setup some stack space and enter the test code.
* Assume everthing except the return value is garbage when we
* Assume everything except the return value is garbage when we
* return, we won't need it.
*/
adrp x0, stack_end

View file

@ -86,7 +86,7 @@ int main(int argc, char *argv[argc])
}
ptr_to_heap++;
}
ml_printf("r/w to heap upto %p\n", ptr_to_heap);
ml_printf("r/w to heap up to %p\n", ptr_to_heap);
ml_printf("Passed HeapInfo checks\n");
return 0;