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xilinx_axi*: Re-implemented interconnect
Re-implemented the interconnect between the Xilinx AXI ethernet and DMA controllers. A QOM interface "stream" is created, for the two stream interfaces. As per Edgars request, this is designed to be more generic than AXI-stream, so in the future we may see more clients of this interface beyond AXI stream. This is based primarily on Paolos original refactoring of the interconnect. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
This commit is contained in:
Peter A. G. Crosthwaite
Edgar E. Iglesias
parent
346fe0c4c0
commit
669b498301
8 changed files with 139 additions and 107 deletions
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@ -29,7 +29,7 @@
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#include "qemu-log.h"
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#include "qdev-addr.h"
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#include "xilinx_axidma.h"
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#include "stream.h"
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#define D(x)
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@ -77,7 +77,7 @@ enum {
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SDESC_STATUS_COMPLETE = (1 << 31)
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};
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struct AXIStream {
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struct Stream {
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QEMUBH *bh;
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ptimer_state *ptimer;
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qemu_irq irq;
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@ -94,9 +94,9 @@ struct XilinxAXIDMA {
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SysBusDevice busdev;
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MemoryRegion iomem;
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uint32_t freqhz;
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void *dmach;
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StreamSlave *tx_dev;
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struct AXIStream streams[2];
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struct Stream streams[2];
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};
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/*
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@ -113,27 +113,27 @@ static inline int stream_desc_eof(struct SDesc *d)
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return d->control & SDESC_CTRL_EOF;
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}
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static inline int stream_resetting(struct AXIStream *s)
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static inline int stream_resetting(struct Stream *s)
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{
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return !!(s->regs[R_DMACR] & DMACR_RESET);
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}
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static inline int stream_running(struct AXIStream *s)
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static inline int stream_running(struct Stream *s)
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{
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return s->regs[R_DMACR] & DMACR_RUNSTOP;
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}
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static inline int stream_halted(struct AXIStream *s)
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static inline int stream_halted(struct Stream *s)
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{
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return s->regs[R_DMASR] & DMASR_HALTED;
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}
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static inline int stream_idle(struct AXIStream *s)
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static inline int stream_idle(struct Stream *s)
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{
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return !!(s->regs[R_DMASR] & DMASR_IDLE);
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}
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static void stream_reset(struct AXIStream *s)
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static void stream_reset(struct Stream *s)
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{
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s->regs[R_DMASR] = DMASR_HALTED; /* starts up halted. */
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s->regs[R_DMACR] = 1 << 16; /* Starts with one in compl threshold. */
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@ -159,7 +159,7 @@ static void stream_desc_show(struct SDesc *d)
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}
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#endif
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static void stream_desc_load(struct AXIStream *s, target_phys_addr_t addr)
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static void stream_desc_load(struct Stream *s, target_phys_addr_t addr)
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{
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struct SDesc *d = &s->desc;
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int i;
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@ -176,7 +176,7 @@ static void stream_desc_load(struct AXIStream *s, target_phys_addr_t addr)
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}
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}
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static void stream_desc_store(struct AXIStream *s, target_phys_addr_t addr)
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static void stream_desc_store(struct Stream *s, target_phys_addr_t addr)
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{
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struct SDesc *d = &s->desc;
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int i;
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@ -192,7 +192,7 @@ static void stream_desc_store(struct AXIStream *s, target_phys_addr_t addr)
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cpu_physical_memory_write(addr, (void *) d, sizeof *d);
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}
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static void stream_update_irq(struct AXIStream *s)
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static void stream_update_irq(struct Stream *s)
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{
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unsigned int pending, mask, irq;
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@ -204,7 +204,7 @@ static void stream_update_irq(struct AXIStream *s)
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qemu_set_irq(s->irq, !!irq);
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}
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static void stream_reload_complete_cnt(struct AXIStream *s)
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static void stream_reload_complete_cnt(struct Stream *s)
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{
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unsigned int comp_th;
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comp_th = (s->regs[R_DMACR] >> 16) & 0xff;
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@ -213,14 +213,14 @@ static void stream_reload_complete_cnt(struct AXIStream *s)
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static void timer_hit(void *opaque)
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{
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struct AXIStream *s = opaque;
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struct Stream *s = opaque;
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stream_reload_complete_cnt(s);
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s->regs[R_DMASR] |= DMASR_DLY_IRQ;
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stream_update_irq(s);
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}
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static void stream_complete(struct AXIStream *s)
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static void stream_complete(struct Stream *s)
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{
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unsigned int comp_delay;
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@ -240,8 +240,8 @@ static void stream_complete(struct AXIStream *s)
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}
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}
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static void stream_process_mem2s(struct AXIStream *s,
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struct XilinxDMAConnection *dmach)
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static void stream_process_mem2s(struct Stream *s,
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StreamSlave *tx_dev)
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{
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uint32_t prev_d;
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unsigned char txbuf[16 * 1024];
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@ -276,7 +276,7 @@ static void stream_process_mem2s(struct AXIStream *s,
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s->pos += txlen;
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if (stream_desc_eof(&s->desc)) {
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xlx_dma_push_to_client(dmach, txbuf, s->pos, app);
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stream_push(tx_dev, txbuf, s->pos, app);
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s->pos = 0;
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stream_complete(s);
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}
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@ -295,7 +295,7 @@ static void stream_process_mem2s(struct AXIStream *s,
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}
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}
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static void stream_process_s2mem(struct AXIStream *s,
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static void stream_process_s2mem(struct Stream *s,
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unsigned char *buf, size_t len, uint32_t *app)
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{
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uint32_t prev_d;
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@ -351,11 +351,11 @@ static void stream_process_s2mem(struct AXIStream *s,
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}
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}
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static
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void axidma_push(void *opaque, unsigned char *buf, size_t len, uint32_t *app)
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static void
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axidma_push(StreamSlave *obj, unsigned char *buf, size_t len, uint32_t *app)
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{
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struct XilinxAXIDMA *d = opaque;
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struct AXIStream *s = &d->streams[1];
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struct XilinxAXIDMA *d = FROM_SYSBUS(typeof(*d), SYS_BUS_DEVICE(obj));
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struct Stream *s = &d->streams[1];
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if (!app) {
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hw_error("No stream app data!\n");
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@ -368,7 +368,7 @@ static uint64_t axidma_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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struct XilinxAXIDMA *d = opaque;
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struct AXIStream *s;
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struct Stream *s;
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uint32_t r = 0;
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int sid;
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@ -403,7 +403,7 @@ static void axidma_write(void *opaque, target_phys_addr_t addr,
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uint64_t value, unsigned size)
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{
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struct XilinxAXIDMA *d = opaque;
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struct AXIStream *s;
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struct Stream *s;
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int sid;
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sid = streamid_from_addr(addr);
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@ -440,7 +440,7 @@ static void axidma_write(void *opaque, target_phys_addr_t addr,
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s->regs[addr] = value;
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s->regs[R_DMASR] &= ~DMASR_IDLE; /* Not idle. */
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if (!sid) {
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stream_process_mem2s(s, d->dmach);
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stream_process_mem2s(s, d->tx_dev);
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}
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break;
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default:
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@ -466,12 +466,6 @@ static int xilinx_axidma_init(SysBusDevice *dev)
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sysbus_init_irq(dev, &s->streams[0].irq);
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sysbus_init_irq(dev, &s->streams[1].irq);
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if (!s->dmach) {
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hw_error("Unconnected DMA channel.\n");
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}
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xlx_dma_connect_dma(s->dmach, s, axidma_push);
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memory_region_init_io(&s->iomem, &axidma_ops, s,
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"xlnx.axi-dma", R_MAX * 4 * 2);
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sysbus_init_mmio(dev, &s->iomem);
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@ -486,9 +480,16 @@ static int xilinx_axidma_init(SysBusDevice *dev)
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return 0;
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}
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static void xilinx_axidma_initfn(Object *obj)
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{
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struct XilinxAXIDMA *s = FROM_SYSBUS(typeof(*s), SYS_BUS_DEVICE(obj));
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object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE,
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(Object **) &s->tx_dev, NULL);
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}
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static Property axidma_properties[] = {
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DEFINE_PROP_UINT32("freqhz", struct XilinxAXIDMA, freqhz, 50000000),
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DEFINE_PROP_PTR("dmach", struct XilinxAXIDMA, dmach),
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DEFINE_PROP_END_OF_LIST(),
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};
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@ -496,9 +497,11 @@ static void axidma_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
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k->init = xilinx_axidma_init;
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dc->props = axidma_properties;
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ssc->push = axidma_push;
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}
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static TypeInfo axidma_info = {
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@ -506,6 +509,11 @@ static TypeInfo axidma_info = {
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(struct XilinxAXIDMA),
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.class_init = axidma_class_init,
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.instance_init = xilinx_axidma_initfn,
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.interfaces = (InterfaceInfo[]) {
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{ TYPE_STREAM_SLAVE },
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{ }
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}
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};
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static void xilinx_axidma_register_types(void)
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