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hw/riscv: add IOMMU HPM trace events

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Add a handful of trace events to allow for an easier time debugging the
HPM feature.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250224190826.1858473-11-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2025-02-24 16:08:25 -03:00 • committed by Alistair Francis
parent 3b1d07b627
commit 66975d9cd7
2 changed files with 15 additions and 0 deletions
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10
hw/riscv/riscv-iommu-hpm.c
View file

@ -39,6 +39,8 @@ uint64_t riscv_iommu_hpmcycle_read(RISCVIOMMUState *s)
const uint64_t ctr_prev = s->hpmcycle_prev;
const uint64_t ctr_val = s->hpmcycle_val;
trace_riscv_iommu_hpm_read(cycle, inhibit, ctr_prev, ctr_val);
if (get_field(inhibit, RISCV_IOMMU_IOCOUNTINH_CY)) {
/*
* Counter should not increment if inhibit bit is set. We can't really
@ -61,6 +63,8 @@ static void hpm_incr_ctr(RISCVIOMMUState *s, uint32_t ctr_idx)
cntr_val = ldq_le_p(&s->regs_rw[RISCV_IOMMU_REG_IOHPMCTR_BASE + off]);
stq_le_p(&s->regs_rw[RISCV_IOMMU_REG_IOHPMCTR_BASE + off], cntr_val + 1);
trace_riscv_iommu_hpm_incr_ctr(cntr_val);
/* Handle the overflow scenario. */
if (cntr_val == UINT64_MAX) {
/*
@ -244,6 +248,8 @@ void riscv_iommu_process_iocntinh_cy(RISCVIOMMUState *s, bool prev_cy_inh)
return;
}
trace_riscv_iommu_hpm_iocntinh_cy(prev_cy_inh);
if (!(inhibit & RISCV_IOMMU_IOCOUNTINH_CY)) {
/*
* Cycle counter is enabled. Just start the timer again and update
@ -268,6 +274,8 @@ void riscv_iommu_process_hpmcycle_write(RISCVIOMMUState *s)
const uint64_t val = riscv_iommu_reg_get64(s, RISCV_IOMMU_REG_IOHPMCYCLES);
const uint32_t ovf = riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_IOCOUNTOVF);
trace_riscv_iommu_hpm_cycle_write(ovf, val);
/*
* Clear OF bit in IOCNTOVF if it's being cleared in IOHPMCYCLES register.
*/
@ -352,6 +360,8 @@ void riscv_iommu_process_hpmevt_write(RISCVIOMMUState *s, uint32_t evt_reg)
return;
}
trace_riscv_iommu_hpm_evt_write(ctr_idx, ovf, val);
/* Clear OF bit in IOCNTOVF if it's being cleared in IOHPMEVT register. */
if (get_field(ovf, BIT(ctr_idx + 1)) &&
!get_field(val, RISCV_IOMMU_IOHPMEVT_OF)) {