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https://github.com/Motorhead1991/qemu.git
synced 2025-08-04 16:23:55 -06:00
sparc update (Blue Swirl)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1350 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
c44644bb96
commit
66321a11a4
5 changed files with 153 additions and 169 deletions
134
hw/lance.c
134
hw/lance.c
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@ -1,7 +1,7 @@
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/*
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* QEMU Lance emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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@ -26,20 +26,24 @@
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/* debug LANCE card */
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//#define DEBUG_LANCE
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#ifdef DEBUG_LANCE
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#define DPRINTF(fmt, args...) \
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do { printf("LANCE: " fmt , ##args); } while (0)
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#else
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#define DPRINTF(fmt, args...)
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#endif
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#ifndef LANCE_LOG_TX_BUFFERS
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#define LANCE_LOG_TX_BUFFERS 4
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#define LANCE_LOG_RX_BUFFERS 4
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#endif
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#define CRC_POLYNOMIAL_BE 0x04c11db7UL /* Ethernet CRC, big endian */
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#define CRC_POLYNOMIAL_LE 0xedb88320UL /* Ethernet CRC, little endian */
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#define LE_CSR0 0
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#define LE_CSR1 1
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#define LE_CSR2 2
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#define LE_CSR3 3
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#define LE_MAXREG (LE_CSR3 + 1)
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#define LE_NREGS (LE_CSR3 + 1)
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#define LE_MAXREG LE_CSR3
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#define LE_RDP 0
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#define LE_RAP 1
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@ -148,21 +152,12 @@ struct lance_init_block {
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#define LEDMA_REGS 4
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#define LEDMA_MAXADDR (LEDMA_REGS * 4 - 1)
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#if 0
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/* Structure to describe the current status of DMA registers on the Sparc */
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struct sparc_dma_registers {
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uint32_t cond_reg; /* DMA condition register */
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uint32_t st_addr; /* Start address of this transfer */
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uint32_t cnt; /* How many bytes to transfer */
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uint32_t dma_test; /* DMA test register */
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};
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#endif
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typedef struct LANCEState {
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NetDriverState *nd;
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uint32_t leptr;
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uint16_t addr;
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uint16_t regs[LE_MAXREG];
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uint16_t regs[LE_NREGS];
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uint8_t phys[6]; /* mac address */
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int irq;
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unsigned int rxptr, txptr;
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@ -177,7 +172,7 @@ static void lance_reset(void *opaque)
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memcpy(s->phys, s->nd->macaddr, 6);
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s->rxptr = 0;
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s->txptr = 0;
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memset(s->regs, 0, LE_MAXREG * 2);
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memset(s->regs, 0, LE_NREGS * 2);
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s->regs[LE_CSR0] = LE_C0_STOP;
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memset(s->ledmaregs, 0, LEDMA_REGS * 4);
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}
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@ -190,10 +185,13 @@ static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr)
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saddr = addr & LE_MAXREG;
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switch (saddr >> 1) {
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case LE_RDP:
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DPRINTF("read dreg[%d] = %4.4x\n", s->addr, s->regs[s->addr]);
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return s->regs[s->addr];
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case LE_RAP:
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DPRINTF("read areg = %4.4x\n", s->addr);
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return s->addr;
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default:
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DPRINTF("read unknown(%d)\n", saddr>>1);
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break;
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}
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return 0;
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@ -208,6 +206,7 @@ static void lance_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val
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saddr = addr & LE_MAXREG;
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switch (saddr >> 1) {
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case LE_RDP:
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DPRINTF("write dreg[%d] = %4.4x\n", s->addr, val);
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switch(s->addr) {
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case LE_CSR0:
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if (val & LE_C0_STOP) {
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@ -242,12 +241,6 @@ static void lance_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val
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}
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s->regs[LE_CSR0] = reg;
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// trigger bits
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//if (val & LE_C0_TDMD)
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if ((s->regs[LE_CSR0] & LE_C0_INTR) && (s->regs[LE_CSR0] & LE_C0_INEA))
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pic_set_irq(s->irq, 1);
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break;
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case LE_CSR1:
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s->leptr = (s->leptr & 0xffff0000) | (val & 0xffff);
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@ -263,10 +256,12 @@ static void lance_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val
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}
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break;
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case LE_RAP:
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if (val < LE_MAXREG)
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DPRINTF("write areg = %4.4x\n", val);
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if (val < LE_NREGS)
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s->addr = val;
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break;
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default:
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DPRINTF("write unknown(%d) = %4.4x\n", saddr>>1, val);
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break;
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}
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lance_send(s);
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@ -292,7 +287,7 @@ static int lance_can_receive(void *opaque)
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uint32_t dmaptr = s->leptr + s->ledmaregs[3];
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struct lance_init_block *ib;
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int i;
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uint16_t temp;
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uint8_t temp8;
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if ((s->regs[LE_CSR0] & LE_C0_STOP) == LE_C0_STOP)
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return 0;
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@ -300,18 +295,13 @@ static int lance_can_receive(void *opaque)
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ib = (void *) iommu_translate(dmaptr);
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for (i = 0; i < RX_RING_SIZE; i++) {
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cpu_physical_memory_read((uint32_t)&ib->brx_ring[i].rmd1_bits, (void *) &temp, 1);
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temp &= 0xff;
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if (temp == (LE_R1_OWN)) {
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#ifdef DEBUG_LANCE
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fprintf(stderr, "lance: can receive %d\n", RX_BUFF_SIZE);
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#endif
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cpu_physical_memory_read((uint32_t)&ib->brx_ring[i].rmd1_bits, (void *) &temp8, 1);
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if (temp8 == (LE_R1_OWN)) {
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DPRINTF("can receive %d\n", RX_BUFF_SIZE);
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return RX_BUFF_SIZE;
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}
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}
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#ifdef DEBUG_LANCE
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fprintf(stderr, "lance: cannot receive\n");
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#endif
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DPRINTF("cannot receive\n");
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return 0;
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}
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@ -322,9 +312,11 @@ static void lance_receive(void *opaque, const uint8_t *buf, int size)
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LANCEState *s = opaque;
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uint32_t dmaptr = s->leptr + s->ledmaregs[3];
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struct lance_init_block *ib;
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unsigned int i, old_rxptr, j;
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uint16_t temp;
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unsigned int i, old_rxptr;
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uint16_t temp16;
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uint8_t temp8;
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DPRINTF("receive size %d\n", size);
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if ((s->regs[LE_CSR0] & LE_C0_STOP) == LE_C0_STOP)
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return;
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@ -332,27 +324,19 @@ static void lance_receive(void *opaque, const uint8_t *buf, int size)
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old_rxptr = s->rxptr;
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for (i = s->rxptr; i != ((old_rxptr - 1) & RX_RING_MOD_MASK); i = (i + 1) & RX_RING_MOD_MASK) {
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cpu_physical_memory_read((uint32_t)&ib->brx_ring[i].rmd1_bits, (void *) &temp, 1);
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if (temp == (LE_R1_OWN)) {
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cpu_physical_memory_read((uint32_t)&ib->brx_ring[i].rmd1_bits, (void *) &temp8, 1);
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if (temp8 == (LE_R1_OWN)) {
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s->rxptr = (s->rxptr + 1) & RX_RING_MOD_MASK;
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temp = size;
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bswap16s(&temp);
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cpu_physical_memory_write((uint32_t)&ib->brx_ring[i].mblength, (void *) &temp, 2);
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#if 0
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temp16 = size + 4;
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bswap16s(&temp16);
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cpu_physical_memory_write((uint32_t)&ib->brx_ring[i].mblength, (void *) &temp16, 2);
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cpu_physical_memory_write((uint32_t)&ib->rx_buf[i], buf, size);
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#else
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for (j = 0; j < size; j++) {
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cpu_physical_memory_write(((uint32_t)&ib->rx_buf[i]) + j, &buf[j], 1);
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}
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#endif
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temp = LE_R1_POK;
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cpu_physical_memory_write((uint32_t)&ib->brx_ring[i].rmd1_bits, (void *) &temp, 1);
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temp8 = LE_R1_POK;
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cpu_physical_memory_write((uint32_t)&ib->brx_ring[i].rmd1_bits, (void *) &temp8, 1);
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s->regs[LE_CSR0] |= LE_C0_RINT | LE_C0_INTR;
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if ((s->regs[LE_CSR0] & LE_C0_INTR) && (s->regs[LE_CSR0] & LE_C0_INEA))
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if (s->regs[LE_CSR0] & LE_C0_INEA)
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pic_set_irq(s->irq, 1);
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#ifdef DEBUG_LANCE
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fprintf(stderr, "lance: got packet, len %d\n", size);
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#endif
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DPRINTF("got packet, len %d\n", size);
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return;
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}
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}
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@ -363,40 +347,36 @@ static void lance_send(void *opaque)
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LANCEState *s = opaque;
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uint32_t dmaptr = s->leptr + s->ledmaregs[3];
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struct lance_init_block *ib;
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unsigned int i, old_txptr, j;
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uint16_t temp;
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unsigned int i, old_txptr;
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uint16_t temp16;
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uint8_t temp8;
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char pkt_buf[PKT_BUF_SZ];
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DPRINTF("sending packet? (csr0 %4.4x)\n", s->regs[LE_CSR0]);
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if ((s->regs[LE_CSR0] & LE_C0_STOP) == LE_C0_STOP)
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return;
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ib = (void *) iommu_translate(dmaptr);
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DPRINTF("sending packet? (dmaptr %8.8x) (ib %p) (btx_ring %p)\n", dmaptr, ib, &ib->btx_ring);
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old_txptr = s->txptr;
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for (i = s->txptr; i != ((old_txptr - 1) & TX_RING_MOD_MASK); i = (i + 1) & TX_RING_MOD_MASK) {
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cpu_physical_memory_read((uint32_t)&ib->btx_ring[i].tmd1_bits, (void *) &temp, 1);
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if (temp == (LE_T1_POK|LE_T1_OWN)) {
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cpu_physical_memory_read((uint32_t)&ib->btx_ring[i].length, (void *) &temp, 2);
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bswap16s(&temp);
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temp = (~temp) + 1;
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#if 0
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cpu_physical_memory_read((uint32_t)&ib->tx_buf[i], pkt_buf, temp);
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#else
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for (j = 0; j < temp; j++) {
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cpu_physical_memory_read((uint32_t)&ib->tx_buf[i] + j, &pkt_buf[j], 1);
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}
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#endif
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#ifdef DEBUG_LANCE
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fprintf(stderr, "lance: sending packet, len %d\n", temp);
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#endif
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qemu_send_packet(s->nd, pkt_buf, temp);
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temp = LE_T1_POK;
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cpu_physical_memory_write((uint32_t)&ib->btx_ring[i].tmd1_bits, (void *) &temp, 1);
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cpu_physical_memory_read((uint32_t)&ib->btx_ring[i].tmd1_bits, (void *) &temp8, 1);
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if (temp8 == (LE_T1_POK|LE_T1_OWN)) {
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cpu_physical_memory_read((uint32_t)&ib->btx_ring[i].length, (void *) &temp16, 2);
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bswap16s(&temp16);
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temp16 = (~temp16) + 1;
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cpu_physical_memory_read((uint32_t)&ib->tx_buf[i], pkt_buf, temp16);
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DPRINTF("sending packet, len %d\n", temp16);
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qemu_send_packet(s->nd, pkt_buf, temp16);
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temp8 = LE_T1_POK;
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cpu_physical_memory_write((uint32_t)&ib->btx_ring[i].tmd1_bits, (void *) &temp8, 1);
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s->txptr = (s->txptr + 1) & TX_RING_MOD_MASK;
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s->regs[LE_CSR0] |= LE_C0_TINT | LE_C0_INTR;
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}
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}
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if ((s->regs[LE_CSR0] & LE_C0_INTR) && (s->regs[LE_CSR0] & LE_C0_INEA))
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pic_set_irq(s->irq, 1);
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}
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static uint32_t ledma_mem_readl(void *opaque, target_phys_addr_t addr)
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@ -436,7 +416,7 @@ static void lance_save(QEMUFile *f, void *opaque)
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qemu_put_be32s(f, &s->leptr);
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qemu_put_be16s(f, &s->addr);
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for (i = 0; i < LE_MAXREG; i ++)
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for (i = 0; i < LE_NREGS; i ++)
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qemu_put_be16s(f, &s->regs[i]);
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qemu_put_buffer(f, s->phys, 6);
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qemu_put_be32s(f, &s->irq);
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@ -454,7 +434,7 @@ static int lance_load(QEMUFile *f, void *opaque, int version_id)
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qemu_get_be32s(f, &s->leptr);
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qemu_get_be16s(f, &s->addr);
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for (i = 0; i < LE_MAXREG; i ++)
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for (i = 0; i < LE_NREGS; i ++)
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qemu_get_be16s(f, &s->regs[i]);
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qemu_get_buffer(f, s->phys, 6);
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qemu_get_be32s(f, &s->irq);
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@ -476,7 +456,7 @@ void lance_init(NetDriverState *nd, int irq, uint32_t leaddr, uint32_t ledaddr)
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s->irq = irq;
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lance_io_memory = cpu_register_io_memory(0, lance_mem_read, lance_mem_write, s);
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cpu_register_physical_memory(leaddr, 8, lance_io_memory);
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cpu_register_physical_memory(leaddr, 4, lance_io_memory);
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ledma_io_memory = cpu_register_io_memory(0, ledma_mem_read, ledma_mem_write, s);
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cpu_register_physical_memory(ledaddr, 16, ledma_io_memory);
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