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https://github.com/Motorhead1991/qemu.git
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sparc update (Blue Swirl)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1350 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
c44644bb96
commit
66321a11a4
5 changed files with 153 additions and 169 deletions
97
hw/iommu.c
97
hw/iommu.c
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@ -1,7 +1,7 @@
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/*
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* QEMU SPARC iommu emulation
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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@ -26,30 +26,14 @@
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/* debug iommu */
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//#define DEBUG_IOMMU
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/* The IOMMU registers occupy three pages in IO space. */
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struct iommu_regs {
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/* First page */
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volatile unsigned long control; /* IOMMU control */
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volatile unsigned long base; /* Physical base of iopte page table */
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volatile unsigned long _unused1[3];
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volatile unsigned long tlbflush; /* write only */
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volatile unsigned long pageflush; /* write only */
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volatile unsigned long _unused2[1017];
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/* Second page */
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volatile unsigned long afsr; /* Async-fault status register */
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volatile unsigned long afar; /* Async-fault physical address */
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volatile unsigned long _unused3[2];
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volatile unsigned long sbuscfg0; /* SBUS configuration registers, per-slot */
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volatile unsigned long sbuscfg1;
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volatile unsigned long sbuscfg2;
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volatile unsigned long sbuscfg3;
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volatile unsigned long mfsr; /* Memory-fault status register */
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volatile unsigned long mfar; /* Memory-fault physical address */
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volatile unsigned long _unused4[1014];
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/* Third page */
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volatile unsigned long mid; /* IOMMU module-id */
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};
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#ifdef DEBUG_IOMMU
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#define DPRINTF(fmt, args...) \
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do { printf("IOMMU: " fmt , ##args); } while (0)
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#else
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#define DPRINTF(fmt, args...)
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#endif
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#define IOMMU_NREGS (3*4096)
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#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
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#define IOMMU_CTRL_VERS 0x0f000000 /* Version */
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#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
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@ -63,43 +47,6 @@ struct iommu_regs {
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#define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
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#define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
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#define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
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#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after transaction */
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#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than 12.8 us. */
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#define IOMMU_AFSR_BE 0x10000000 /* Write access received error acknowledge */
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#define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
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#define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
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#define IOMMU_AFSR_RESV 0x00f00000 /* Reserver, forced to 0x8 by hardware */
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#define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
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#define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
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#define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
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#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when bypass enabled */
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#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
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#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
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#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
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produced by this device as pure
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physical. */
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#define IOMMU_MFSR_ERR 0x80000000 /* One or more of PERR1 or PERR0 */
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#define IOMMU_MFSR_S 0x01000000 /* Sparc was in supervisor mode */
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#define IOMMU_MFSR_CPU 0x00800000 /* CPU transaction caused parity error */
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#define IOMMU_MFSR_ME 0x00080000 /* Multiple parity errors occurred */
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#define IOMMU_MFSR_PERR 0x00006000 /* high bit indicates parity error occurred
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on the even word of the access, low bit
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indicated odd word caused the parity error */
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#define IOMMU_MFSR_BM 0x00001000 /* Error occurred while in boot mode */
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#define IOMMU_MFSR_C 0x00000800 /* Address causing error was marked cacheable */
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#define IOMMU_MFSR_RTYP 0x000000f0 /* Memory request transaction type */
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#define IOMMU_MID_SBAE 0x001f0000 /* SBus arbitration enable */
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#define IOMMU_MID_SE 0x00100000 /* Enables SCSI/ETHERNET arbitration */
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#define IOMMU_MID_SB3 0x00080000 /* Enable SBUS device 3 arbitration */
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#define IOMMU_MID_SB2 0x00040000 /* Enable SBUS device 2 arbitration */
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#define IOMMU_MID_SB1 0x00020000 /* Enable SBUS device 1 arbitration */
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#define IOMMU_MID_SB0 0x00010000 /* Enable SBUS device 0 arbitration */
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#define IOMMU_MID_MID 0x0000000f /* Module-id, hardcoded to 0x8 */
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/* The format of an iopte in the page tables */
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#define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */
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#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
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@ -113,7 +60,7 @@ struct iommu_regs {
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typedef struct IOMMUState {
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uint32_t addr;
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uint32_t regs[sizeof(struct iommu_regs)];
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uint32_t regs[IOMMU_NREGS];
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uint32_t iostart;
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} IOMMUState;
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@ -125,6 +72,7 @@ static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
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saddr = (addr - s->addr) >> 2;
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switch (saddr) {
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default:
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DPRINTF("read reg[%d] = %x\n", saddr, s->regs[saddr]);
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return s->regs[saddr];
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break;
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}
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@ -137,6 +85,7 @@ static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val
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uint32_t saddr;
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saddr = (addr - s->addr) >> 2;
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DPRINTF("write reg[%d] = %x\n", saddr, val);
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switch (saddr) {
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case 0:
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switch (val & IOMMU_CTRL_RNGE) {
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@ -166,6 +115,7 @@ static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val
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s->iostart = 0x80000000;
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break;
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}
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DPRINTF("iostart = %x\n", s->iostart);
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/* Fall through */
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default:
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s->regs[saddr] = val;
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@ -188,13 +138,17 @@ static CPUWriteMemoryFunc *iommu_mem_write[3] = {
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uint32_t iommu_translate_local(void *opaque, uint32_t addr)
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{
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IOMMUState *s = opaque;
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uint32_t *iopte = (void *)(s->regs[1] << 4), pa;
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uint32_t iopte, pa, tmppte;
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iopte += ((addr - s->iostart) >> PAGE_SHIFT);
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cpu_physical_memory_read((uint32_t)iopte, (void *) &pa, 4);
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iopte = s->regs[1] << 4;
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addr &= ~s->iostart;
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iopte += (addr >> (PAGE_SHIFT - 2)) & ~3;
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cpu_physical_memory_read(iopte, (void *) &pa, 4);
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bswap32s(&pa);
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pa = (pa & IOPTE_PAGE) << 4; /* Loose higher bits of 36 */
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return pa + (addr & PAGE_MASK);
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tmppte = pa;
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pa = ((pa & IOPTE_PAGE) << 4) + (addr & PAGE_MASK);
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DPRINTF("xlate dva %x => pa %x (iopte[%x] = %x)\n", addr, pa, iopte, tmppte);
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return pa;
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}
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static void iommu_save(QEMUFile *f, void *opaque)
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@ -203,7 +157,7 @@ static void iommu_save(QEMUFile *f, void *opaque)
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int i;
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qemu_put_be32s(f, &s->addr);
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for (i = 0; i < sizeof(struct iommu_regs); i += 4)
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for (i = 0; i < IOMMU_NREGS; i++)
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qemu_put_be32s(f, &s->regs[i]);
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qemu_put_be32s(f, &s->iostart);
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}
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@ -217,7 +171,7 @@ static int iommu_load(QEMUFile *f, void *opaque, int version_id)
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return -EINVAL;
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qemu_get_be32s(f, &s->addr);
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for (i = 0; i < sizeof(struct iommu_regs); i += 4)
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for (i = 0; i < IOMMU_NREGS; i++)
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qemu_put_be32s(f, &s->regs[i]);
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qemu_get_be32s(f, &s->iostart);
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@ -228,7 +182,7 @@ static void iommu_reset(void *opaque)
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{
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IOMMUState *s = opaque;
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memset(s->regs, 0, sizeof(struct iommu_regs));
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memset(s->regs, 0, IOMMU_NREGS * 4);
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s->iostart = 0;
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}
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@ -244,8 +198,7 @@ void *iommu_init(uint32_t addr)
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s->addr = addr;
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iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s);
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cpu_register_physical_memory(addr, sizeof(struct iommu_regs),
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iommu_io_memory);
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cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
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register_savevm("iommu", addr, 1, iommu_save, iommu_load, s);
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qemu_register_reset(iommu_reset, s);
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