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target-arm: Correctly handle PSTATE.SS when taking exception to AArch32

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When an exception is taken to AArch32, we must clear the PSTATE.SS
bit for the exception handler, and must also ensure that the SS bit
is not set in the value saved to SPSR_<mode>. Achieve both of these
aims by clearing the bit in uncached_cpsr before saving it to the SPSR.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
This commit is contained in:
Peter Maydell 2014-08-19 18:56:26 +01:00
parent 4051e12c5d
commit 662cefb775
1 changed files with 4 additions and 0 deletions
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4
target-arm/helper.c
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@ -3550,6 +3550,10 @@ void arm_cpu_do_interrupt(CPUState *cs)
addr += env->cp15.vbar_el[1]; addr += env->cp15.vbar_el[1];
} }
switch_mode (env, new_mode); switch_mode (env, new_mode);
/* For exceptions taken to AArch32 we must clear the SS bit in both
* PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
*/
env->uncached_cpsr &= ~PSTATE_SS;
env->spsr = cpsr_read(env); env->spsr = cpsr_read(env);
/* Clear IT bits. */ /* Clear IT bits. */
env->condexec_bits = 0; env->condexec_bits = 0;