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PowerPC SPE extension fix: must always preserve GPR high bits when

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running in 32 bits mode.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3631 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
j_mayer 2007-11-12 23:29:14 +00:00
parent 4f6cf9e839
commit 65d6c0f33c
3 changed files with 6 additions and 6 deletions
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6
target-ppc/translate.c
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@ -5822,7 +5822,7 @@ GEN_VR_STX(vxl, 0x07, 0x0F);
/*** SPE extension ***/
/* Register moves */
#if TARGET_GPR_BITS < 64
#if !defined(TARGET_PPC64)
GEN32(gen_op_load_gpr64_T0, gen_op_load_gpr64_T0_gpr);
GEN32(gen_op_load_gpr64_T1, gen_op_load_gpr64_T1_gpr);
@ -5836,7 +5836,7 @@ GEN32(gen_op_store_T1_gpr64, gen_op_store_T1_gpr64_gpr);
GEN32(gen_op_store_T2_gpr64, gen_op_store_T2_gpr64_gpr);
#endif
#else /* TARGET_GPR_BITS < 64 */
#else /* !defined(TARGET_PPC64) */
/* No specific load/store functions: GPRs are already 64 bits */
#define gen_op_load_gpr64_T0 gen_op_load_gpr_T0
@ -5851,7 +5851,7 @@ GEN32(gen_op_store_T2_gpr64, gen_op_store_T2_gpr64_gpr);
#define gen_op_store_T2_gpr64 gen_op_store_T2_gpr
#endif
#endif /* TARGET_GPR_BITS < 64 */
#endif /* !defined(TARGET_PPC64) */
#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \