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target-arm queue:
* gdbstub: Correct misparsing of vCont C/S requests * openrisc: Move pic_cpu code into CPU object proper * nios2: Move IIC code into CPU object proper * Improve reporting of ROM overlap errors * xlnx-versal: Add USB support * hw/misc/zynq_slcr: Avoid #DIV/0! error * Numonyx: Fix dummy cycles and check for SPI mode on cmds -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAl/YwVIZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3lOpD/9FjasMvZqYeanyNlv+4Swk 4MFeYouIzXKSFu9tj5eDTHzN1TJl5iSwhkIcr9NBqxppuv2eqzxfWWMEfCZ06pxz BR2HoSlSLUih8cKpu40cQg0TTMEOGEOV9RAHtt8vSGE0FesoiXG2ORUPcxm3NxbN l9XZ1x3Yb5ZLqVZViFjlZ5gXnTzJ//uPEzbl7N9+pa0mXDKvmvwAl19DLmF6N2Jj D+gmrLGeEbkJ358RGO/VF7r/1bOkrhwKrb8MzeqFRmjIqaOGbGqs/71+amiSjS8n hC1HKf6KQOLrklMVaYg1pRxHLbHpQR+haeeX4Xt9jxx8EUrwXojlyaD8p4V9Hcu8 L5haTIBhPrnTkUfHZYL0qYkqRpzbNq97oX2Gmk967FfsZME5fxNa3kS6zM0GkIBx YKghaZtFInAFODUbG1hHdUc+WbvfQDhj/mBQ6wWw669vYpoab/3nfVq8YVoupVM/ RntcqpBfqtGgPzuJ2dJEEsm6QlK4SZaGlmPkz542OzcHxw3SgeqkbIuDW/CtNI+b c5PgX0C2S2AnFAAHURnsXdqt6+O01FZqOU7SCLjmwrBrpDG69lum+JLCqXFe9iMW XgrTrxyPIcz5+Bv63AqKcm6rpcQs5ekwmLLEjT0OJtr+5ef9MeRil0aChj1j4i+2 H/82yKR4JWW1egEvTJhskQ== =lHZA -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20201215' into staging target-arm queue: * gdbstub: Correct misparsing of vCont C/S requests * openrisc: Move pic_cpu code into CPU object proper * nios2: Move IIC code into CPU object proper * Improve reporting of ROM overlap errors * xlnx-versal: Add USB support * hw/misc/zynq_slcr: Avoid #DIV/0! error * Numonyx: Fix dummy cycles and check for SPI mode on cmds # gpg: Signature made Tue 15 Dec 2020 13:59:46 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20201215: hw/block/m25p80: Fix Numonyx fast read dummy cycle count hw/block/m25p80: Check SPI mode before running some Numonyx commands hw/block/m25p80: Fix when VCFG XIP bit is set for Numonyx hw/block/m25p80: Make Numonyx config field names more accurate hw/misc/zynq_slcr: Avoid #DIV/0! error arm: xlnx-versal: Connect usb to virt-versal usb: xlnx-usb-subsystem: Add xilinx usb subsystem usb: Add DWC3 model usb: Add versal-usb2-ctrl-regs module elf_ops.h: Be more verbose with ROM blob names elf_ops.h: Don't truncate name of the ROM blobs we create hw/core/loader.c: Improve reporting of ROM overlap errors hw/core/loader.c: Track last-seen ROM in rom_check_and_register_reset() target/nios2: Use deposit32() to update ipending register target/nios2: Move nios2_check_interrupts() into target/nios2 target/nios2: Move IIC code into CPU object proper target/openrisc: Move pic_cpu code into CPU object proper hw/openrisc/openrisc_sim: Abstract out "get IRQ x of CPU y" hw/openrisc/openrisc_sim: Use IRQ splitter when connecting IRQ to multiple CPUs gdbstub: Correct misparsing of vCont C/S requests Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
657ee88ef3
32 changed files with 1557 additions and 304 deletions
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@ -64,6 +64,26 @@ static void nios2_cpu_reset(DeviceState *dev)
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#endif
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}
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#ifndef CONFIG_USER_ONLY
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static void nios2_cpu_set_irq(void *opaque, int irq, int level)
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{
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Nios2CPU *cpu = opaque;
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CPUNios2State *env = &cpu->env;
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CPUState *cs = CPU(cpu);
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env->regs[CR_IPENDING] = deposit32(env->regs[CR_IPENDING], irq, 1, !!level);
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env->irq_pending = env->regs[CR_IPENDING] & env->regs[CR_IENABLE];
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if (env->irq_pending && (env->regs[CR_STATUS] & CR_STATUS_PIE)) {
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env->irq_pending = 0;
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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} else if (!env->irq_pending) {
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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}
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#endif
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static void nios2_cpu_initfn(Object *obj)
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{
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Nios2CPU *cpu = NIOS2_CPU(obj);
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@ -72,6 +92,15 @@ static void nios2_cpu_initfn(Object *obj)
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#if !defined(CONFIG_USER_ONLY)
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mmu_init(&cpu->env);
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/*
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* These interrupt lines model the IIC (internal interrupt
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* controller). QEMU does not currently support the EIC
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* (external interrupt controller) -- if we did it would be
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* a separate device in hw/intc with a custom interface to
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* the CPU, and boards using it would not wire up these IRQ lines.
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*/
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qdev_init_gpio_in_named(DEVICE(cpu), nios2_cpu_set_irq, "IRQ", 32);
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#endif
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}
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@ -201,9 +201,6 @@ void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
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MMUAccessType access_type,
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int mmu_idx, uintptr_t retaddr);
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qemu_irq *nios2_cpu_pic_init(Nios2CPU *cpu);
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void nios2_check_interrupts(CPUNios2State *env);
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void do_nios2_semihosting(CPUNios2State *env);
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#define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU
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@ -36,6 +36,15 @@ void helper_mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
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mmu_write(env, rn, v);
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}
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static void nios2_check_interrupts(CPUNios2State *env)
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{
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if (env->irq_pending &&
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(env->regs[CR_STATUS] & CR_STATUS_PIE)) {
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env->irq_pending = 0;
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cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HARD);
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}
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}
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void helper_check_interrupts(CPUNios2State *env)
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{
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qemu_mutex_lock_iothread();
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@ -65,6 +65,34 @@ static void openrisc_cpu_reset(DeviceState *dev)
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#endif
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}
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#ifndef CONFIG_USER_ONLY
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static void openrisc_cpu_set_irq(void *opaque, int irq, int level)
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{
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OpenRISCCPU *cpu = (OpenRISCCPU *)opaque;
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CPUState *cs = CPU(cpu);
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uint32_t irq_bit;
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if (irq > 31 || irq < 0) {
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return;
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}
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irq_bit = 1U << irq;
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if (level) {
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cpu->env.picsr |= irq_bit;
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} else {
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cpu->env.picsr &= ~irq_bit;
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}
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if (cpu->env.picsr & cpu->env.picmr) {
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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} else {
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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cpu->env.picsr = 0;
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}
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}
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#endif
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static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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@ -88,6 +116,10 @@ static void openrisc_cpu_initfn(Object *obj)
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OpenRISCCPU *cpu = OPENRISC_CPU(obj);
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cpu_set_cpustate_pointers(cpu);
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#ifndef CONFIG_USER_ONLY
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qdev_init_gpio_in_named(DEVICE(cpu), openrisc_cpu_set_irq, "IRQ", NR_IRQS);
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#endif
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}
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/* CPU models */
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@ -293,7 +293,6 @@ typedef struct CPUOpenRISCState {
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uint32_t picmr; /* Interrupt mask register */
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uint32_t picsr; /* Interrupt contrl register*/
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#endif
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void *irq[32]; /* Interrupt irq input */
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} CPUOpenRISCState;
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/**
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