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hw/intc/arm_gic: introduce a first-cpu-index property

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This introduces a first-cpu-index property to the arm-gic, as some SOCs
could have two separate GIC (ie: the zynqmp).

Signed-off-by: Clément Chigot <chigot@adacore.com>
Message-id: 20250526085523.809003-3-chigot@adacore.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: slightly expanded comment documenting GIC property]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Frederic Konrad 2025-05-26 10:55:21 +02:00 • committed by Peter Maydell
parent 5dc8e4e892
commit 6559e7ad8e
4 changed files with 7 additions and 1 deletions
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3
include/hw/intc/arm_gic.h
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@ -27,6 +27,9 @@
* implement the security extensions
* + QOM property "has-virtualization-extensions": set true if the GIC should
* implement the virtualization extensions
* + QOM property "first-cpu-index": index of the first cpu attached to the
* GIC (default 0). The CPUs connected to the GIC are assumed to be
* first-cpu-index, first-cpu-index + 1, ... first-cpu-index + num-cpu - 1.
* + unnamed GPIO inputs: (where P is number of SPIs, i.e. num-irq - 32)
* [0..P-1] SPIs
* [P..P+31] PPIs for CPU 0

2
include/hw/intc/arm_gic_common.h
View file

@ -129,6 +129,8 @@ struct GICState {
uint32_t num_lrs;
uint32_t num_cpu;
/* cpu_index of the first CPU, attached to this GIC. */
uint32_t first_cpu_index;
MemoryRegion iomem; /* Distributor */
/* This is just so we can have an opaque pointer which identifies