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Fourth RISC-V PR for 6.1 release
- Code cleanups - Documentation improvements - Hypervisor extension improvements with hideleg and hedeleg - sifive_u fixes - OpenTitan register layout updates - Fix coverity issue -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmDv4DgACgkQIeENKd+X cFS//Qf8CY5vc8fEq34mwGKPm/ETD3F5Vp1L5r/S4K1NbGp3Qkj/TlA3o5LOa8jw PMRp/26k/q/1dXffFTIXKOJy/sKFYNlon042UkK7mD5y6hSDPkJa0Qp5JxDyrw4j vN/+BNI6Wwg404eOqNnwr2Do7JGgOYS/S9clGoUV6YfIjJkUHQCvGzTCm0dD2tCf HYVXdwZWzSysLifv5rMMZM9P+ALg3VKyWpXHHqb4EG3l18VZ6PLpO0chA7vtVV88 3EXQ97QEKl1n/RSqHjqQRxIz20r+rje/1kArIA27sFL6kaBah0BHpl6d161MtuS5 8aaKhPY3VfUf+BU1elI7UBg14+SHfQ== =FIxa -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210715' into staging Fourth RISC-V PR for 6.1 release - Code cleanups - Documentation improvements - Hypervisor extension improvements with hideleg and hedeleg - sifive_u fixes - OpenTitan register layout updates - Fix coverity issue # gpg: Signature made Thu 15 Jul 2021 08:14:00 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20210715: hw/riscv/boot: Check the error of fdt_pack() hw/riscv: opentitan: Add the flash alias hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri char: ibex_uart: Update the register layout hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned hw/riscv: sifive_u: Correct the CLINT timebase frequency docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot target/riscv: hardwire bits in hideleg and hedeleg docs/system: riscv: Add documentation for virt machine docs/system: riscv: Fix CLINT name in the sifive_u doc target/riscv: csr: Remove redundant check in fp csr read/write routines target/riscv: pmp: Fix some typos Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
65388f4044
11 changed files with 257 additions and 75 deletions
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@ -47,13 +47,13 @@ The user provided DTB should have the following requirements:
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QEMU follows below truth table to select which payload to execute:
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===== ========== =======
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-bios -kernel payload
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===== ========== =======
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N N HSS
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Y don't care HSS
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N Y kernel
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===== ========== =======
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===== ========== ========== =======
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-bios -kernel -dtb payload
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===== ========== ========== =======
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N N don't care HSS
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Y don't care don't care HSS
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N Y Y kernel
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===== ========== ========== =======
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The memory is set to 1537 MiB by default which is the minimum required high
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memory size by HSS. A sanity check on ram size is performed in the machine
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@ -106,4 +106,44 @@ HSS output is on the first serial port (stdio) and U-Boot outputs on the
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second serial port. U-Boot will automatically load the Linux kernel from
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the SD card image.
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Direct Kernel Boot
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------------------
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Sometimes we just want to test booting a new kernel, and transforming the
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kernel image to the format required by the HSS bootflow is tedious. We can
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use '-kernel' for direct kernel booting just like other RISC-V machines do.
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In this mode, the OpenSBI fw_dynamic BIOS image for 'generic' platform is
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used to boot an S-mode payload like U-Boot or OS kernel directly.
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For example, the following commands show building a U-Boot image from U-Boot
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mainline v2021.07 for the Microchip Icicle Kit board:
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.. code-block:: bash
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$ export CROSS_COMPILE=riscv64-linux-
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$ make microchip_mpfs_icicle_defconfig
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Then we can boot the machine by:
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.. code-block:: bash
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$ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 -m 2G \
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-sd path/to/sdcard.img \
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-nic user,model=cadence_gem \
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-nic tap,ifname=tap,model=cadence_gem,script=no \
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-display none -serial stdio \
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-kernel path/to/u-boot/build/dir/u-boot.bin \
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-dtb path/to/u-boot/build/dir/u-boot.dtb
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CAVEATS:
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* Check the "stdout-path" property in the /chosen node in the DTB to determine
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which serial port is used for the serial console, e.g.: if the console is set
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to the second serial port, change to use "-serial null -serial stdio".
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* The default U-Boot configuration uses CONFIG_OF_SEPARATE hence the ELF image
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``u-boot`` cannot be passed to "-kernel" as it does not contain the DTB hence
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``u-boot.bin`` has to be used which does contain one. To use the ELF image,
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we need to change to CONFIG_OF_EMBED or CONFIG_OF_PRIOR_STAGE.
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.. _HSS: https://github.com/polarfire-soc/hart-software-services
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@ -11,7 +11,7 @@ The ``sifive_u`` machine supports the following devices:
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* 1 E51 / E31 core
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* Up to 4 U54 / U34 cores
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* Core Level Interruptor (CLINT)
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* Core Local Interruptor (CLINT)
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* Platform-Level Interrupt Controller (PLIC)
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* Power, Reset, Clock, Interrupt (PRCI)
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* L2 Loosely Integrated Memory (L2-LIM)
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138
docs/system/riscv/virt.rst
Normal file
138
docs/system/riscv/virt.rst
Normal file
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@ -0,0 +1,138 @@
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'virt' Generic Virtual Platform (``virt``)
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==========================================
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The `virt` board is a platform which does not correspond to any real hardware;
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it is designed for use in virtual machines. It is the recommended board type
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if you simply want to run a guest such as Linux and do not care about
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reproducing the idiosyncrasies and limitations of a particular bit of
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real-world hardware.
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Supported devices
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-----------------
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The ``virt`` machine supports the following devices:
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* Up to 8 generic RV32GC/RV64GC cores, with optional extensions
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* Core Local Interruptor (CLINT)
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* Platform-Level Interrupt Controller (PLIC)
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* CFI parallel NOR flash memory
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* 1 NS16550 compatible UART
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* 1 Google Goldfish RTC
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* 1 SiFive Test device
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* 8 virtio-mmio transport devices
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* 1 generic PCIe host bridge
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* The fw_cfg device that allows a guest to obtain data from QEMU
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Note that the default CPU is a generic RV32GC/RV64GC. Optional extensions
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can be enabled via command line parameters, e.g.: ``-cpu rv64,x-h=true``
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enables the hypervisor extension for RV64.
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Hardware configuration information
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----------------------------------
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The ``virt`` machine automatically generates a device tree blob ("dtb")
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which it passes to the guest, if there is no ``-dtb`` option. This provides
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information about the addresses, interrupt lines and other configuration of
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the various devices in the system. Guest software should discover the devices
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that are present in the generated DTB.
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If users want to provide their own DTB, they can use the ``-dtb`` option.
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These DTBs should have the following requirements:
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* The number of subnodes of the /cpus node should match QEMU's ``-smp`` option
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* The /memory reg size should match QEMU’s selected ram_size via ``-m``
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* Should contain a node for the CLINT device with a compatible string
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"riscv,clint0" if using with OpenSBI BIOS images
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Boot options
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------------
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The ``virt`` machine can start using the standard -kernel functionality
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for loading a Linux kernel, a VxWorks kernel, an S-mode U-Boot bootloader
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with the default OpenSBI firmware image as the -bios. It also supports
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the recommended RISC-V bootflow: U-Boot SPL (M-mode) loads OpenSBI fw_dynamic
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firmware and U-Boot proper (S-mode), using the standard -bios functionality.
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Running Linux kernel
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--------------------
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Linux mainline v5.12 release is tested at the time of writing. To build a
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Linux mainline kernel that can be booted by the ``virt`` machine in
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64-bit mode, simply configure the kernel using the defconfig configuration:
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.. code-block:: bash
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$ export ARCH=riscv
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$ export CROSS_COMPILE=riscv64-linux-
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$ make defconfig
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$ make
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To boot the newly built Linux kernel in QEMU with the ``virt`` machine:
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.. code-block:: bash
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$ qemu-system-riscv64 -M virt -smp 4 -m 2G \
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-display none -serial stdio \
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-kernel arch/riscv/boot/Image \
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-initrd /path/to/rootfs.cpio \
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-append "root=/dev/ram"
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To build a Linux mainline kernel that can be booted by the ``virt`` machine
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in 32-bit mode, use the rv32_defconfig configuration. A patch is required to
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fix the 32-bit boot issue for Linux kernel v5.12.
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.. code-block:: bash
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$ export ARCH=riscv
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$ export CROSS_COMPILE=riscv64-linux-
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$ curl https://patchwork.kernel.org/project/linux-riscv/patch/20210627135117.28641-1-bmeng.cn@gmail.com/mbox/ > riscv.patch
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$ git am riscv.patch
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$ make rv32_defconfig
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$ make
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Replace ``qemu-system-riscv64`` with ``qemu-system-riscv32`` in the command
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line above to boot the 32-bit Linux kernel. A rootfs image containing 32-bit
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applications shall be used in order for kernel to boot to user space.
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Running U-Boot
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--------------
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U-Boot mainline v2021.04 release is tested at the time of writing. To build an
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S-mode U-Boot bootloader that can be booted by the ``virt`` machine, use
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the qemu-riscv64_smode_defconfig with similar commands as described above for Linux:
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.. code-block:: bash
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$ export CROSS_COMPILE=riscv64-linux-
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$ make qemu-riscv64_smode_defconfig
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Boot the 64-bit U-Boot S-mode image directly:
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.. code-block:: bash
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$ qemu-system-riscv64 -M virt -smp 4 -m 2G \
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-display none -serial stdio \
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-kernel /path/to/u-boot.bin
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To test booting U-Boot SPL which in M-mode, which in turn loads a FIT image
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that bundles OpenSBI fw_dynamic firmware and U-Boot proper (S-mode) together,
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build the U-Boot images using riscv64_spl_defconfig:
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.. code-block:: bash
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$ export CROSS_COMPILE=riscv64-linux-
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$ export OPENSBI=/path/to/opensbi-riscv64-generic-fw_dynamic.bin
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$ make qemu-riscv64_spl_defconfig
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The minimal QEMU commands to run U-Boot SPL are:
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.. code-block:: bash
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$ qemu-system-riscv64 -M virt -smp 4 -m 2G \
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-display none -serial stdio \
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-bios /path/to/u-boot-spl \
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-device loader,file=/path/to/u-boot.itb,addr=0x80200000
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To test 32-bit U-Boot images, switch to use qemu-riscv32_smode_defconfig and
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riscv32_spl_defconfig builds, and replace ``qemu-system-riscv64`` with
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``qemu-system-riscv32`` in the command lines above to boot the 32-bit U-Boot.
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@ -69,6 +69,7 @@ undocumented; you can get a complete list by running
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riscv/microchip-icicle-kit
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riscv/shakti-c
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riscv/sifive_u
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riscv/virt
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RISC-V CPU firmware
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-------------------
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