motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-03 07:43:54 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/arm: Expose Aarch64 helpers unconditionally

Browse source 
At worst, for 32-bit arm binary, using these methods will
now produce a link time error, instead of a compile time one.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20250403235821.9909-37-philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2025-04-04 01:58:18 +02:00 • committed by Richard Henderson
parent 63de8825af
commit 652d19a642
1 changed files with 0 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

2
target/arm/internals.h
View file

@ -1808,7 +1808,6 @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
return (1ULL << 31) | ((1ULL << pmu_num_counters(env)) - 1);
}
#ifdef TARGET_AARCH64
GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cpu, int base_reg);
int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg);
int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg);
@ -1826,7 +1825,6 @@ void aarch64_max_tcg_initfn(Object *obj);
void aarch64_add_pauth_properties(Object *obj);
void aarch64_add_sve_properties(Object *obj);
void aarch64_add_sme_properties(Object *obj);
#endif
/* Read the CONTROL register as the MRS instruction would. */
uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure);