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target/riscv: remove cpu->cfg.ext_j

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Create a new "j" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVJ. Instances of cpu->cfg.ext_j and similar are
replaced with riscv_has_ext(env, RVJ).

Remove the old "j" property and 'ext_j' from RISCVCPUConfig.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-16-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2023-04-06 15:03:46 -03:00 • committed by Alistair Francis
parent b5c042e8a0
commit 64f4b541c5
2 changed files with 3 additions and 4 deletions
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6
target/riscv/cpu.c
View file

@ -1178,7 +1178,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
if (riscv_cpu_cfg(env)->ext_v) { if (riscv_cpu_cfg(env)->ext_v) {
ext |= RVV; ext |= RVV;
} }
if (riscv_cpu_cfg(env)->ext_j) { if (riscv_has_ext(env, RVJ)) {
ext |= RVJ; ext |= RVJ;
} }
@ -1511,6 +1511,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
.misa_bit = RVU, .enabled = true}, .misa_bit = RVU, .enabled = true},
{.name = "h", .description = "Hypervisor", {.name = "h", .description = "Hypervisor",
.misa_bit = RVH, .enabled = true}, .misa_bit = RVH, .enabled = true},
{.name = "x-j", .description = "Dynamic translated languages",
.misa_bit = RVJ, .enabled = false},
}; };
static void riscv_cpu_add_misa_properties(Object *cpu_obj) static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@ -1607,7 +1609,6 @@ static Property riscv_cpu_extensions[] = {
/* These are experimental so mark with 'x-' */ /* These are experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false), DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false),
DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false), DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false),
@ -1648,7 +1649,6 @@ static void register_cpu_props(Object *obj)
*/ */
if (cpu->env.misa_ext != 0) { if (cpu->env.misa_ext != 0) {
cpu->cfg.ext_v = misa_ext & RVV; cpu->cfg.ext_v = misa_ext & RVV;
cpu->cfg.ext_j = misa_ext & RVJ;
/* /*
* We don't want to set the default riscv_cpu_extensions * We don't want to set the default riscv_cpu_extensions

1
target/riscv/cpu.h
View file

@ -423,7 +423,6 @@ typedef struct {
struct RISCVCPUConfig { struct RISCVCPUConfig {
bool ext_g; bool ext_g;
bool ext_j;
bool ext_v; bool ext_v;
bool ext_zba; bool ext_zba;
bool ext_zbb; bool ext_zbb;