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target/ppc: 405: Program exception cleanup

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The 405 Program Interrupt does not set SRR1 with any diagnostic bits,
just a clean copy of the MSR.

We're using the BookE Exception Syndrome Register which is different
from the 405.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: restored SPR_40x_ESR settings ]
Message-Id: <20220118184448.852996-14-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Fabiano Rosas 2022-01-28 13:15:05 +01:00 • committed by Cédric Le Goater
parent 35f579f5c2
commit 64e62cfbec
1 changed files with 4 additions and 15 deletions
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19
target/ppc/excp_helper.c
View file

@ -483,30 +483,19 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
env->error_code = 0; env->error_code = 0;
return; return;
} }
env->spr[SPR_40x_ESR] = ESR_FP;
/*
* FP exceptions always have NIP pointing to the faulting
* instruction, so always use store_next and claim we are
* precise in the MSR.
*/
msr |= 0x00100000;
env->spr[SPR_BOOKE_ESR] = ESR_FP;
break; break;
case POWERPC_EXCP_INVAL: case POWERPC_EXCP_INVAL:
trace_ppc_excp_inval(env->nip); trace_ppc_excp_inval(env->nip);
msr |= 0x00080000; env->spr[SPR_40x_ESR] = ESR_PIL;
env->spr[SPR_BOOKE_ESR] = ESR_PIL;
break; break;
case POWERPC_EXCP_PRIV: case POWERPC_EXCP_PRIV:
msr |= 0x00040000; env->spr[SPR_40x_ESR] = ESR_PPR;
env->spr[SPR_BOOKE_ESR] = ESR_PPR;
break; break;
case POWERPC_EXCP_TRAP: case POWERPC_EXCP_TRAP:
msr |= 0x00020000; env->spr[SPR_40x_ESR] = ESR_PTR;
env->spr[SPR_BOOKE_ESR] = ESR_PTR;
break; break;
default: default:
/* Should never occur */
cpu_abort(cs, "Invalid program exception %d. Aborting\n", cpu_abort(cs, "Invalid program exception %d. Aborting\n",
env->error_code); env->error_code);
break; break;