mirror of
https://github.com/Motorhead1991/qemu.git
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ppc-7.0 queue
* ppc/pnv fixes * PMU EBB support * target/ppc: PowerISA Vector/VSX instruction batch * ppc/pnv: Extension of the powernv10 machine with XIVE2 ans PHB5 models * spapr allocation cleanups -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmIfTloACgkQUaNDx8/7 7KFSjg/+PzZn81n2WiDE5HCORc5L/nwFMv8zevBNpHZn3LE1nTfzEV0BqekiyWc4 nsMix9soXlYX86u7HzCZI212jPWbf6z+4ACI40uQh8U7t45CXkmKi5x8kosPbwqa d7iOiDv76k8f2c3Uv9ynmYk3TZOfrA5Ua79P+ZE09EKnIr6dYmcGCq6EYm6KN6p8 hoZ97DbyT5loQ1x7/pIO10Wr84xvoEGYzqm6+TKFTsyBNSaXjzXNIJegxHDuR0iz D9YFb/w3WzBR9EORRzasvuZFI3yGcgy/WuWJUrb2VC8G+TTe7IlJsAFoCNyoysh7 FbtL1vTmHPh7XSfn34sB1x4wqPHaohrS4/zCN1l1eeEU+giTBXGhPULEypCDqHgn SD1DLRwVRqT0uH5SqEGPl2eYaccs0MHflD2YWS5HdOdBYE9jic8jQDv8TZlfqhzp x9B1b/dg3nlz7yaOj3LFw7ohN2IlU7o66QqcKytO3phdp6a2z4OoFvv6jcnEqYwi YnL8ScUeXqheDfA/fh1BF4gAZdSf655Kvk7MbGwBLwFq2jqygP8Ca2ODp03NYhB0 qb3sM08fy7CSIdwaDySePDkrWcHU/XeVhRN6Gj8W1g8ZH9Z7/iSLiP4hZjEqvXNC zoM1ut0CkrHpZzPZv3+ZGxzr0A+fDZGub0rp7W6BbPzYyiChuIk= =kWv5 -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220302' into staging ppc-7.0 queue * ppc/pnv fixes * PMU EBB support * target/ppc: PowerISA Vector/VSX instruction batch * ppc/pnv: Extension of the powernv10 machine with XIVE2 ans PHB5 models * spapr allocation cleanups # gpg: Signature made Wed 02 Mar 2022 11:00:42 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * remotes/legoater/tags/pull-ppc-20220302: (87 commits) hw/ppc/spapr_vio.c: use g_autofree in spapr_dt_vdevice() hw/ppc/spapr_rtas.c: use g_autofree in rtas_ibm_get_system_parameter() spapr_pci_nvlink2.c: use g_autofree in spapr_phb_nvgpu_ram_populate_dt() hw/ppc/spapr_numa.c: simplify spapr_numa_write_assoc_lookup_arrays() hw/ppc/spapr_drc.c: use g_autofree in spapr_drc_by_index() hw/ppc/spapr_drc.c: use g_autofree in spapr_dr_connector_new() hw/ppc/spapr_drc.c: use g_autofree in drc_unrealize() hw/ppc/spapr_drc.c: use g_autofree in drc_realize() hw/ppc/spapr_drc.c: use g_auto in spapr_dt_drc() hw/ppc/spapr_caps.c: use g_autofree in spapr_caps_add_properties() hw/ppc/spapr_caps.c: use g_autofree in spapr_cap_get_string() hw/ppc/spapr_caps.c: use g_autofree in spapr_cap_set_string() hw/ppc/spapr.c: fail early if no firmware found in machine_init() hw/ppc/spapr.c: use g_autofree in spapr_dt_chosen() pnv/xive2: Add support for 8bits thread id pnv/xive2: Add support for automatic save&restore xive2: Add a get_config() handler for the router configuration pnv/xive2: Add support XIVE2 P9-compat mode (or Gen1) ppc/pnv: add XIVE Gen2 TIMA support pnv/xive2: Introduce new capability bits ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
64ada298b9
51 changed files with 7740 additions and 951 deletions
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@ -49,6 +49,7 @@ typedef struct PnvPhb4DMASpace {
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*/
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#define TYPE_PNV_PHB4_ROOT_BUS "pnv-phb4-root"
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#define TYPE_PNV_PHB4_ROOT_PORT "pnv-phb4-root-port"
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#define TYPE_PNV_PHB5_ROOT_PORT "pnv-phb5-root-port"
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typedef struct PnvPHB4RootPort {
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PCIESlot parent_obj;
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@ -206,4 +207,15 @@ struct PnvPhb4PecClass {
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const char *rp_model;
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};
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/*
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* POWER10 definitions
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*/
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#define PNV_PHB5_VERSION 0x000000a500000001ull
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#define PNV_PHB5_DEVICE_ID 0x0652
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#define TYPE_PNV_PHB5_PEC "pnv-phb5-pec"
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#define PNV_PHB5_PEC(obj) \
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OBJECT_CHECK(PnvPhb4PecState, (obj), TYPE_PNV_PHB5_PEC)
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#endif /* PCI_HOST_PNV_PHB4_H */
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@ -220,11 +220,14 @@
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#define PHB_PAPR_ERR_INJ_MASK_MMIO PPC_BITMASK(16, 63)
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#define PHB_ETU_ERR_SUMMARY 0x2c8
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#define PHB_INT_NOTIFY_ADDR 0x300
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#define PHB_INT_NOTIFY_ADDR_64K PPC_BIT(1) /* P10 */
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#define PHB_INT_NOTIFY_INDEX 0x308
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/* Fundamental register set B */
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#define PHB_VERSION 0x800
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#define PHB_CTRLR 0x810
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#define PHB_CTRLR_IRQ_PQ_DISABLE PPC_BIT(9) /* P10 */
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#define PHB_CTRLR_IRQ_ABT_MODE PPC_BIT(10) /* P10 */
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#define PHB_CTRLR_IRQ_PGSZ_64K PPC_BIT(11)
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#define PHB_CTRLR_IRQ_STORE_EOI PPC_BIT(12)
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#define PHB_CTRLR_MMIO_RD_STRICT PPC_BIT(13)
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@ -125,10 +125,22 @@ struct Pnv10Chip {
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PnvChip parent_obj;
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/*< public >*/
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PnvXive2 xive;
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Pnv9Psi psi;
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PnvLpcController lpc;
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PnvOCC occ;
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PnvHomer homer;
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uint32_t nr_quads;
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PnvQuad *quads;
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#define PNV10_CHIP_MAX_PEC 2
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PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC];
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};
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#define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
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#define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
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struct PnvChipClass {
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/*< private >*/
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SysBusDeviceClass parent_class;
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@ -329,10 +341,37 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);
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#define PNV10_LPCM_SIZE 0x0000000100000000ull
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#define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull)
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#define PNV10_XIVE2_IC_SIZE 0x0000000002000000ull
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#define PNV10_XIVE2_IC_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030200000000ull)
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#define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull
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#define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull)
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#define PNV10_PSIHB_SIZE 0x0000000000100000ull
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#define PNV10_PSIHB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203000000ull)
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#define PNV10_XIVE2_TM_SIZE 0x0000000000040000ull
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#define PNV10_XIVE2_TM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203180000ull)
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#define PNV10_XIVE2_NVC_SIZE 0x0000000008000000ull
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#define PNV10_XIVE2_NVC_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030208000000ull)
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#define PNV10_XIVE2_NVPG_SIZE 0x0000010000000000ull
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#define PNV10_XIVE2_NVPG_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006040000000000ull)
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#define PNV10_XIVE2_ESB_SIZE 0x0000010000000000ull
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#define PNV10_XIVE2_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006050000000000ull)
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#define PNV10_XIVE2_END_SIZE 0x0000020000000000ull
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#define PNV10_XIVE2_END_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006060000000000ull)
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#define PNV10_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
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#define PNV10_OCC_COMMON_AREA_BASE 0x300fff800000ull
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#define PNV10_OCC_SENSOR_BASE(chip) (PNV10_OCC_COMMON_AREA_BASE + \
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PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
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#define PNV10_HOMER_SIZE 0x0000000000400000ull
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#define PNV10_HOMER_BASE(chip) \
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(0x300ffd800000ll + ((uint64_t)(chip)->chip_id) * PNV10_HOMER_SIZE)
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#endif /* PPC_PNV_H */
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@ -32,6 +32,9 @@ DECLARE_INSTANCE_CHECKER(PnvHomer, PNV8_HOMER,
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#define TYPE_PNV9_HOMER TYPE_PNV_HOMER "-POWER9"
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DECLARE_INSTANCE_CHECKER(PnvHomer, PNV9_HOMER,
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TYPE_PNV9_HOMER)
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#define TYPE_PNV10_HOMER TYPE_PNV_HOMER "-POWER10"
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DECLARE_INSTANCE_CHECKER(PnvHomer, PNV10_HOMER,
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TYPE_PNV10_HOMER)
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struct PnvHomer {
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DeviceState parent;
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@ -32,6 +32,8 @@ DECLARE_INSTANCE_CHECKER(PnvOCC, PNV8_OCC,
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#define TYPE_PNV9_OCC TYPE_PNV_OCC "-POWER9"
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DECLARE_INSTANCE_CHECKER(PnvOCC, PNV9_OCC,
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TYPE_PNV9_OCC)
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#define TYPE_PNV10_OCC TYPE_PNV_OCC "-POWER10"
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DECLARE_INSTANCE_CHECKER(PnvOCC, PNV10_OCC, TYPE_PNV10_OCC)
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#define PNV_OCC_SENSOR_DATA_BLOCK_OFFSET 0x00580000
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#define PNV_OCC_SENSOR_DATA_BLOCK_SIZE 0x00025800
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@ -12,6 +12,7 @@
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#include "hw/ppc/xive.h"
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#include "qom/object.h"
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#include "hw/ppc/xive2.h"
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struct PnvChip;
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@ -95,4 +96,74 @@ struct PnvXiveClass {
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void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon);
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/*
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* XIVE2 interrupt controller (POWER10)
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*/
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#define TYPE_PNV_XIVE2 "pnv-xive2"
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OBJECT_DECLARE_TYPE(PnvXive2, PnvXive2Class, PNV_XIVE2);
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typedef struct PnvXive2 {
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Xive2Router parent_obj;
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/* Owning chip */
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struct PnvChip *chip;
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/* XSCOM addresses giving access to the controller registers */
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MemoryRegion xscom_regs;
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MemoryRegion ic_mmio;
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MemoryRegion ic_mmios[8];
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MemoryRegion esb_mmio;
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MemoryRegion end_mmio;
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MemoryRegion nvc_mmio;
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MemoryRegion nvpg_mmio;
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MemoryRegion tm_mmio;
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/* Shortcut values for the Main MMIO regions */
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hwaddr ic_base;
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uint32_t ic_shift;
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hwaddr esb_base;
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uint32_t esb_shift;
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hwaddr end_base;
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uint32_t end_shift;
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hwaddr nvc_base;
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uint32_t nvc_shift;
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hwaddr nvpg_base;
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uint32_t nvpg_shift;
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hwaddr tm_base;
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uint32_t tm_shift;
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/* Interrupt controller registers */
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uint64_t cq_regs[0x40];
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uint64_t vc_regs[0x100];
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uint64_t pc_regs[0x100];
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uint64_t tctxt_regs[0x30];
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/* To change default behavior */
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uint64_t capabilities;
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uint64_t config;
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/* Our XIVE source objects for IPIs and ENDs */
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XiveSource ipi_source;
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Xive2EndSource end_source;
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/*
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* Virtual Structure Descriptor tables
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* These are in a SRAM protected by ECC.
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*/
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uint64_t vsds[9][XIVE_BLOCK_MAX];
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/* Translation tables */
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uint64_t tables[8][XIVE_BLOCK_MAX];
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} PnvXive2;
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typedef struct PnvXive2Class {
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Xive2RouterClass parent_class;
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DeviceRealize parent_realize;
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} PnvXive2Class;
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void pnv_xive2_pic_print_info(PnvXive2 *xive, Monitor *mon);
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#endif /* PPC_PNV_XIVE_H */
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@ -131,6 +131,21 @@ struct PnvXScomInterfaceClass {
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#define PNV10_XSCOM_PSIHB_BASE 0x3011D00
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#define PNV10_XSCOM_PSIHB_SIZE 0x100
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#define PNV10_XSCOM_OCC_BASE PNV9_XSCOM_OCC_BASE
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#define PNV10_XSCOM_OCC_SIZE PNV9_XSCOM_OCC_SIZE
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#define PNV10_XSCOM_PBA_BASE 0x01010CDA
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#define PNV10_XSCOM_PBA_SIZE 0x40
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#define PNV10_XSCOM_XIVE2_BASE 0x2010800
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#define PNV10_XSCOM_XIVE2_SIZE 0x400
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#define PNV10_XSCOM_PEC_NEST_BASE 0x3011800 /* index goes downwards ... */
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#define PNV10_XSCOM_PEC_NEST_SIZE 0x100
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#define PNV10_XSCOM_PEC_PCI_BASE 0x8010800 /* index goes upwards ... */
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#define PNV10_XSCOM_PEC_PCI_SIZE 0x200
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void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp);
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int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset,
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uint64_t xscom_base, uint64_t xscom_size,
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@ -160,7 +160,7 @@ DECLARE_CLASS_CHECKERS(XiveNotifierClass, XIVE_NOTIFIER,
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struct XiveNotifierClass {
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InterfaceClass parent;
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void (*notify)(XiveNotifier *xn, uint32_t lisn);
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void (*notify)(XiveNotifier *xn, uint32_t lisn, bool pq_checked);
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};
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/*
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@ -176,6 +176,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(XiveSource, XIVE_SOURCE)
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*/
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#define XIVE_SRC_H_INT_ESB 0x1 /* ESB managed with hcall H_INT_ESB */
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#define XIVE_SRC_STORE_EOI 0x2 /* Store EOI supported */
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#define XIVE_SRC_PQ_DISABLE 0x4 /* Disable check on the PQ state bits */
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struct XiveSource {
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DeviceState parent;
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@ -278,6 +279,7 @@ uint8_t xive_esb_set(uint8_t *pq, uint8_t value);
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#define XIVE_ESB_STORE_EOI 0x400 /* Store */
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#define XIVE_ESB_LOAD_EOI 0x000 /* Load */
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#define XIVE_ESB_GET 0x800 /* Load */
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#define XIVE_ESB_INJECT 0x800 /* Store */
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#define XIVE_ESB_SET_PQ_00 0xc00 /* Load */
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#define XIVE_ESB_SET_PQ_01 0xd00 /* Load */
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#define XIVE_ESB_SET_PQ_10 0xe00 /* Load */
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@ -385,6 +387,10 @@ struct XiveRouterClass {
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/* XIVE table accessors */
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int (*get_eas)(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
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XiveEAS *eas);
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int (*get_pq)(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
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uint8_t *pq);
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int (*set_pq)(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
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uint8_t *pq);
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int (*get_end)(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
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XiveEND *end);
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int (*write_end)(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
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@ -406,7 +412,7 @@ int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
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XiveNVT *nvt);
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int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
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XiveNVT *nvt, uint8_t word_number);
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void xive_router_notify(XiveNotifier *xn, uint32_t lisn);
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void xive_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked);
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/*
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* XIVE Presenter
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109
include/hw/ppc/xive2.h
Normal file
109
include/hw/ppc/xive2.h
Normal file
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@ -0,0 +1,109 @@
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/*
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* QEMU PowerPC XIVE2 interrupt controller model (POWER10)
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*
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* Copyright (c) 2019-2022, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*
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*/
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#ifndef PPC_XIVE2_H
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#define PPC_XIVE2_H
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#include "hw/ppc/xive2_regs.h"
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/*
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* XIVE2 Router (POWER10)
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*/
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typedef struct Xive2Router {
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SysBusDevice parent;
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XiveFabric *xfb;
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} Xive2Router;
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#define TYPE_XIVE2_ROUTER "xive2-router"
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OBJECT_DECLARE_TYPE(Xive2Router, Xive2RouterClass, XIVE2_ROUTER);
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/*
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* Configuration flags
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*/
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#define XIVE2_GEN1_TIMA_OS 0x00000001
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#define XIVE2_VP_SAVE_RESTORE 0x00000002
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#define XIVE2_THREADID_8BITS 0x00000004
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typedef struct Xive2RouterClass {
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SysBusDeviceClass parent;
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/* XIVE table accessors */
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int (*get_eas)(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
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Xive2Eas *eas);
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int (*get_pq)(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
|
||||
uint8_t *pq);
|
||||
int (*set_pq)(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
|
||||
uint8_t *pq);
|
||||
int (*get_end)(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
|
||||
Xive2End *end);
|
||||
int (*write_end)(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
|
||||
Xive2End *end, uint8_t word_number);
|
||||
int (*get_nvp)(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
|
||||
Xive2Nvp *nvp);
|
||||
int (*write_nvp)(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
|
||||
Xive2Nvp *nvp, uint8_t word_number);
|
||||
uint8_t (*get_block_id)(Xive2Router *xrtr);
|
||||
uint32_t (*get_config)(Xive2Router *xrtr);
|
||||
} Xive2RouterClass;
|
||||
|
||||
int xive2_router_get_eas(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
|
||||
Xive2Eas *eas);
|
||||
int xive2_router_get_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
|
||||
Xive2End *end);
|
||||
int xive2_router_write_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
|
||||
Xive2End *end, uint8_t word_number);
|
||||
int xive2_router_get_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
|
||||
Xive2Nvp *nvp);
|
||||
int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
|
||||
Xive2Nvp *nvp, uint8_t word_number);
|
||||
uint32_t xive2_router_get_config(Xive2Router *xrtr);
|
||||
|
||||
void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked);
|
||||
|
||||
/*
|
||||
* XIVE2 Presenter (POWER10)
|
||||
*/
|
||||
|
||||
int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
|
||||
uint8_t format,
|
||||
uint8_t nvt_blk, uint32_t nvt_idx,
|
||||
bool cam_ignore, uint32_t logic_serv);
|
||||
|
||||
/*
|
||||
* XIVE2 END ESBs (POWER10)
|
||||
*/
|
||||
|
||||
#define TYPE_XIVE2_END_SOURCE "xive2-end-source"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(Xive2EndSource, XIVE2_END_SOURCE)
|
||||
|
||||
typedef struct Xive2EndSource {
|
||||
DeviceState parent;
|
||||
|
||||
uint32_t nr_ends;
|
||||
|
||||
/* ESB memory region */
|
||||
uint32_t esb_shift;
|
||||
MemoryRegion esb_mmio;
|
||||
|
||||
Xive2Router *xrtr;
|
||||
} Xive2EndSource;
|
||||
|
||||
/*
|
||||
* XIVE2 Thread Interrupt Management Area (POWER10)
|
||||
*/
|
||||
|
||||
void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
|
||||
uint64_t value, unsigned size);
|
||||
uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
|
||||
hwaddr offset, unsigned size);
|
||||
|
||||
#endif /* PPC_XIVE2_H */
|
||||
210
include/hw/ppc/xive2_regs.h
Normal file
210
include/hw/ppc/xive2_regs.h
Normal file
|
|
@ -0,0 +1,210 @@
|
|||
/*
|
||||
* QEMU PowerPC XIVE2 internal structure definitions (POWER10)
|
||||
*
|
||||
* Copyright (c) 2019-2022, IBM Corporation.
|
||||
*
|
||||
* This code is licensed under the GPL version 2 or later. See the
|
||||
* COPYING file in the top-level directory.
|
||||
*/
|
||||
|
||||
#ifndef PPC_XIVE2_REGS_H
|
||||
#define PPC_XIVE2_REGS_H
|
||||
|
||||
/*
|
||||
* Thread Interrupt Management Area (TIMA)
|
||||
*
|
||||
* In Gen1 mode (P9 compat mode) word 2 is the same. However in Gen2
|
||||
* mode (P10), the CAM line is slightly different as the VP space was
|
||||
* increased.
|
||||
*/
|
||||
#define TM2_QW0W2_VU PPC_BIT32(0)
|
||||
#define TM2_QW0W2_LOGIC_SERV PPC_BITMASK32(4, 31)
|
||||
#define TM2_QW1W2_VO PPC_BIT32(0)
|
||||
#define TM2_QW1W2_HO PPC_BIT32(1)
|
||||
#define TM2_QW1W2_OS_CAM PPC_BITMASK32(4, 31)
|
||||
#define TM2_QW2W2_VP PPC_BIT32(0)
|
||||
#define TM2_QW2W2_HP PPC_BIT32(1)
|
||||
#define TM2_QW2W2_POOL_CAM PPC_BITMASK32(4, 31)
|
||||
#define TM2_QW3W2_VT PPC_BIT32(0)
|
||||
#define TM2_QW3W2_HT PPC_BIT32(1)
|
||||
#define TM2_QW3W2_LP PPC_BIT32(6)
|
||||
#define TM2_QW3W2_LE PPC_BIT32(7)
|
||||
|
||||
/*
|
||||
* Event Assignment Structure (EAS)
|
||||
*/
|
||||
|
||||
typedef struct Xive2Eas {
|
||||
uint64_t w;
|
||||
#define EAS2_VALID PPC_BIT(0)
|
||||
#define EAS2_END_BLOCK PPC_BITMASK(4, 7) /* Destination EQ block# */
|
||||
#define EAS2_END_INDEX PPC_BITMASK(8, 31) /* Destination EQ index */
|
||||
#define EAS2_MASKED PPC_BIT(32) /* Masked */
|
||||
#define EAS2_END_DATA PPC_BITMASK(33, 63) /* written to the EQ */
|
||||
} Xive2Eas;
|
||||
|
||||
#define xive2_eas_is_valid(eas) (be64_to_cpu((eas)->w) & EAS2_VALID)
|
||||
#define xive2_eas_is_masked(eas) (be64_to_cpu((eas)->w) & EAS2_MASKED)
|
||||
|
||||
void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, Monitor *mon);
|
||||
|
||||
/*
|
||||
* Event Notifification Descriptor (END)
|
||||
*/
|
||||
|
||||
typedef struct Xive2End {
|
||||
uint32_t w0;
|
||||
#define END2_W0_VALID PPC_BIT32(0) /* "v" bit */
|
||||
#define END2_W0_ENQUEUE PPC_BIT32(5) /* "q" bit */
|
||||
#define END2_W0_UCOND_NOTIFY PPC_BIT32(6) /* "n" bit */
|
||||
#define END2_W0_SILENT_ESCALATE PPC_BIT32(7) /* "s" bit */
|
||||
#define END2_W0_BACKLOG PPC_BIT32(8) /* "b" bit */
|
||||
#define END2_W0_PRECL_ESC_CTL PPC_BIT32(9) /* "p" bit */
|
||||
#define END2_W0_UNCOND_ESCALATE PPC_BIT32(10) /* "u" bit */
|
||||
#define END2_W0_ESCALATE_CTL PPC_BIT32(11) /* "e" bit */
|
||||
#define END2_W0_ADAPTIVE_ESC PPC_BIT32(12) /* "a" bit */
|
||||
#define END2_W0_ESCALATE_END PPC_BIT32(13) /* "N" bit */
|
||||
#define END2_W0_FIRMWARE1 PPC_BIT32(16) /* Owned by FW */
|
||||
#define END2_W0_FIRMWARE2 PPC_BIT32(17) /* Owned by FW */
|
||||
#define END2_W0_AEC_SIZE PPC_BITMASK32(18, 19)
|
||||
#define END2_W0_AEG_SIZE PPC_BITMASK32(20, 23)
|
||||
#define END2_W0_EQ_VG_PREDICT PPC_BITMASK32(24, 31) /* Owned by HW */
|
||||
uint32_t w1;
|
||||
#define END2_W1_ESn PPC_BITMASK32(0, 1)
|
||||
#define END2_W1_ESn_P PPC_BIT32(0)
|
||||
#define END2_W1_ESn_Q PPC_BIT32(1)
|
||||
#define END2_W1_ESe PPC_BITMASK32(2, 3)
|
||||
#define END2_W1_ESe_P PPC_BIT32(2)
|
||||
#define END2_W1_ESe_Q PPC_BIT32(3)
|
||||
#define END2_W1_GEN_FLIPPED PPC_BIT32(8)
|
||||
#define END2_W1_GENERATION PPC_BIT32(9)
|
||||
#define END2_W1_PAGE_OFF PPC_BITMASK32(10, 31)
|
||||
uint32_t w2;
|
||||
#define END2_W2_RESERVED PPC_BITMASK32(4, 7)
|
||||
#define END2_W2_EQ_ADDR_HI PPC_BITMASK32(8, 31)
|
||||
uint32_t w3;
|
||||
#define END2_W3_EQ_ADDR_LO PPC_BITMASK32(0, 24)
|
||||
#define END2_W3_QSIZE PPC_BITMASK32(28, 31)
|
||||
uint32_t w4;
|
||||
#define END2_W4_END_BLOCK PPC_BITMASK32(4, 7)
|
||||
#define END2_W4_ESC_END_INDEX PPC_BITMASK32(8, 31)
|
||||
#define END2_W4_ESB_BLOCK PPC_BITMASK32(0, 3)
|
||||
#define END2_W4_ESC_ESB_INDEX PPC_BITMASK32(4, 31)
|
||||
uint32_t w5;
|
||||
#define END2_W5_ESC_END_DATA PPC_BITMASK32(1, 31)
|
||||
uint32_t w6;
|
||||
#define END2_W6_FORMAT_BIT PPC_BIT32(0)
|
||||
#define END2_W6_IGNORE PPC_BIT32(1)
|
||||
#define END2_W6_VP_BLOCK PPC_BITMASK32(4, 7)
|
||||
#define END2_W6_VP_OFFSET PPC_BITMASK32(8, 31)
|
||||
#define END2_W6_VP_OFFSET_GEN1 PPC_BITMASK32(13, 31)
|
||||
uint32_t w7;
|
||||
#define END2_W7_TOPO PPC_BITMASK32(0, 3) /* Owned by HW */
|
||||
#define END2_W7_F0_PRIORITY PPC_BITMASK32(8, 15)
|
||||
#define END2_W7_F1_LOG_SERVER_ID PPC_BITMASK32(4, 31)
|
||||
} Xive2End;
|
||||
|
||||
#define xive2_end_is_valid(end) (be32_to_cpu((end)->w0) & END2_W0_VALID)
|
||||
#define xive2_end_is_enqueue(end) (be32_to_cpu((end)->w0) & END2_W0_ENQUEUE)
|
||||
#define xive2_end_is_notify(end) \
|
||||
(be32_to_cpu((end)->w0) & END2_W0_UCOND_NOTIFY)
|
||||
#define xive2_end_is_backlog(end) (be32_to_cpu((end)->w0) & END2_W0_BACKLOG)
|
||||
#define xive2_end_is_escalate(end) \
|
||||
(be32_to_cpu((end)->w0) & END2_W0_ESCALATE_CTL)
|
||||
#define xive2_end_is_uncond_escalation(end) \
|
||||
(be32_to_cpu((end)->w0) & END2_W0_UNCOND_ESCALATE)
|
||||
#define xive2_end_is_silent_escalation(end) \
|
||||
(be32_to_cpu((end)->w0) & END2_W0_SILENT_ESCALATE)
|
||||
#define xive2_end_is_escalate_end(end) \
|
||||
(be32_to_cpu((end)->w0) & END2_W0_ESCALATE_END)
|
||||
#define xive2_end_is_firmware1(end) \
|
||||
(be32_to_cpu((end)->w0) & END2_W0_FIRMWARE1)
|
||||
#define xive2_end_is_firmware2(end) \
|
||||
(be32_to_cpu((end)->w0) & END2_W0_FIRMWARE2)
|
||||
|
||||
static inline uint64_t xive2_end_qaddr(Xive2End *end)
|
||||
{
|
||||
return ((uint64_t) be32_to_cpu(end->w2) & END2_W2_EQ_ADDR_HI) << 32 |
|
||||
(be32_to_cpu(end->w3) & END2_W3_EQ_ADDR_LO);
|
||||
}
|
||||
|
||||
void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, Monitor *mon);
|
||||
void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width,
|
||||
Monitor *mon);
|
||||
void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx,
|
||||
Monitor *mon);
|
||||
|
||||
/*
|
||||
* Notification Virtual Processor (NVP)
|
||||
*/
|
||||
typedef struct Xive2Nvp {
|
||||
uint32_t w0;
|
||||
#define NVP2_W0_VALID PPC_BIT32(0)
|
||||
#define NVP2_W0_HW PPC_BIT32(7)
|
||||
#define NVP2_W0_ESC_END PPC_BIT32(25) /* 'N' bit 0:ESB 1:END */
|
||||
uint32_t w1;
|
||||
#define NVP2_W1_CO PPC_BIT32(13)
|
||||
#define NVP2_W1_CO_PRIV PPC_BITMASK32(14, 15)
|
||||
#define NVP2_W1_CO_THRID_VALID PPC_BIT32(16)
|
||||
#define NVP2_W1_CO_THRID PPC_BITMASK32(17, 31)
|
||||
uint32_t w2;
|
||||
#define NVP2_W2_CPPR PPC_BITMASK32(0, 7)
|
||||
#define NVP2_W2_IPB PPC_BITMASK32(8, 15)
|
||||
#define NVP2_W2_LSMFB PPC_BITMASK32(16, 23)
|
||||
uint32_t w3;
|
||||
uint32_t w4;
|
||||
#define NVP2_W4_ESC_ESB_BLOCK PPC_BITMASK32(0, 3) /* N:0 */
|
||||
#define NVP2_W4_ESC_ESB_INDEX PPC_BITMASK32(4, 31) /* N:0 */
|
||||
#define NVP2_W4_ESC_END_BLOCK PPC_BITMASK32(4, 7) /* N:1 */
|
||||
#define NVP2_W4_ESC_END_INDEX PPC_BITMASK32(8, 31) /* N:1 */
|
||||
uint32_t w5;
|
||||
#define NVP2_W5_PSIZE PPC_BITMASK32(0, 1)
|
||||
#define NVP2_W5_VP_END_BLOCK PPC_BITMASK32(4, 7)
|
||||
#define NVP2_W5_VP_END_INDEX PPC_BITMASK32(8, 31)
|
||||
uint32_t w6;
|
||||
uint32_t w7;
|
||||
} Xive2Nvp;
|
||||
|
||||
#define xive2_nvp_is_valid(nvp) (be32_to_cpu((nvp)->w0) & NVP2_W0_VALID)
|
||||
#define xive2_nvp_is_hw(nvp) (be32_to_cpu((nvp)->w0) & NVP2_W0_HW)
|
||||
#define xive2_nvp_is_co(nvp) (be32_to_cpu((nvp)->w1) & NVP2_W1_CO)
|
||||
|
||||
/*
|
||||
* The VP number space in a block is defined by the END2_W6_VP_OFFSET
|
||||
* field of the XIVE END. When running in Gen1 mode (P9 compat mode),
|
||||
* the VP space is reduced to (1 << 19) VPs per block
|
||||
*/
|
||||
#define XIVE2_NVP_SHIFT 24
|
||||
#define XIVE2_NVP_COUNT (1 << XIVE2_NVP_SHIFT)
|
||||
|
||||
static inline uint32_t xive2_nvp_cam_line(uint8_t nvp_blk, uint32_t nvp_idx)
|
||||
{
|
||||
return (nvp_blk << XIVE2_NVP_SHIFT) | nvp_idx;
|
||||
}
|
||||
|
||||
static inline uint32_t xive2_nvp_idx(uint32_t cam_line)
|
||||
{
|
||||
return cam_line & ((1 << XIVE2_NVP_SHIFT) - 1);
|
||||
}
|
||||
|
||||
static inline uint32_t xive2_nvp_blk(uint32_t cam_line)
|
||||
{
|
||||
return (cam_line >> XIVE2_NVP_SHIFT) & 0xf;
|
||||
}
|
||||
|
||||
/*
|
||||
* Notification Virtual Group or Crowd (NVG/NVC)
|
||||
*/
|
||||
typedef struct Xive2Nvgc {
|
||||
uint32_t w0;
|
||||
#define NVGC2_W0_VALID PPC_BIT32(0)
|
||||
uint32_t w1;
|
||||
uint32_t w2;
|
||||
uint32_t w3;
|
||||
uint32_t w4;
|
||||
uint32_t w5;
|
||||
uint32_t w6;
|
||||
uint32_t w7;
|
||||
} Xive2Nvgc;
|
||||
|
||||
#endif /* PPC_XIVE2_REGS_H */
|
||||
Loading…
Add table
Add a link
Reference in a new issue