motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-03 15:53:54 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

hw/intc/arm_gicv3: Implement new GICv4 redistributor registers

Browse source 
Implement the new GICv4 redistributor registers: GICR_VPROPBASER
and GICR_VPENDBASER; for the moment we implement these as simple
reads-as-written stubs, together with the necessary migration
and reset handling.

We don't put ID-register checks on the handling of these registers,
because they are all in the only-in-v4 extra register frames, so
they're not accessible in a GICv3.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-24-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2022-04-08 15:15:32 +01:00
parent ae3b3ba15c
commit 641be69745
4 changed files with 102 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

3
include/hw/intc/arm_gicv3_common.h
View file

@ -179,6 +179,9 @@ struct GICv3CPUState {
uint32_t gicr_igrpmodr0;
uint32_t gicr_nsacr;
uint8_t gicr_ipriorityr[GIC_INTERNAL];
/* VLPI_base page registers */
uint64_t gicr_vpropbaser;
uint64_t gicr_vpendbaser;
/* CPU interface */
uint64_t icc_sre_el1;