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xtensa queue 2013-07-29
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.13 (GNU/Linux) iQIcBAABAgAGBQJR9oJeAAoJEFH5zJH4P6BEqzQQAIdlk2X1s6xrPhxiuC0xQmK6 eHoYVVqVy8wQiXXY+NgbTK6VsbEI/2B58lngFKkUiXQggWHIDUytYpcwymZqVSRS 9r+VEwy/sa6R/hAGkl7Igs++bsPEkwQqH2b0kDwX+Mi0sCYXZ6Ihe+kqGBkIjzUO QXvk3LIVF+ESCeroFUOifgAYncMVDN6er8THJnNHUvfP2lAobkYbh4jbBhmOyKJ6 kjh0I/rndEyyF0gVfhzPJpdb5whXBlIwjN1CjvoER3Ax24rnfJcBTuDvhV/vtuZY dPEOiN/ZDyCeowIMuFDxbtdA5oH2nc6Sm2mqk6iB669ki87vn5vLI6nSAp2C5zAY CMPP9JNkhWsBcvjPQOMws/aloru5G2g7ljp7Drd4Ij/gwvlEpAozFtzjhc7QbcMc 6h7spZ01pRqqICimgUHVf6hYZNeRvhQvzybTA9ccIa0yhyTKTpzQwhNWl+6a2O0x 4w6SV3RJ9Z+eftS3MOlMpe7raJMg0F5rJQak73hkc07jDB8iaUsJk/8ZAPzT3Y8x HwbCE6bGU/ipO8xcGpPC4Lc+vY0+CQXJWRq/x/AiY8SAR6QwRvb9h+Sw0T/5/nYg 0D12NV5C33ou5RACXdp76Mpxig2rnusWsAj+XSEU8QLB2/TrJ2hMGIdCXUyajCGy pr3+BwxWdZkKH7N3oi61 =JPm8 -----END PGP SIGNATURE----- Merge remote-tracking branch 'filippov/tags/20130729-xtensa' into staging xtensa queue 2013-07-29 * filippov/tags/20130729-xtensa: target-xtensa: check register window inline target-xtensa: don't generate dead code to access invalid SRs tests/tcg/xtensa: Fix out-of-tree build target-xtensa: avoid double-stopping at breakpoints target-xtensa: add fallthrough markers target-xtensa: add extui unit test Conflicts: configure Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Anthony Liguori
commit
64160cd2a3
6 changed files with 93 additions and 34 deletions
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@ -484,6 +484,7 @@ static inline int cpu_mmu_index(CPUXtensaState *env)
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#define XTENSA_TBFLAG_ICOUNT 0x20
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#define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
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#define XTENSA_TBFLAG_CPENABLE_SHIFT 6
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#define XTENSA_TBFLAG_EXCEPTION 0x4000
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static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
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target_ulong *cs_base, int *flags)
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@ -510,6 +511,9 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
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if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
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*flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
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}
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if (ENV_GET_CPU(env)->singlestep_enabled && env->exception_taken) {
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*flags |= XTENSA_TBFLAG_EXCEPTION;
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}
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}
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#include "exec/cpu-all.h"
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@ -96,6 +96,9 @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
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void HELPER(exception)(CPUXtensaState *env, uint32_t excp)
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{
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env->exception_index = excp;
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if (excp == EXCP_DEBUG) {
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env->exception_taken = 0;
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}
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cpu_loop_exit(env);
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}
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@ -448,8 +451,10 @@ void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr)
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switch (access & PAGE_CACHE_MASK) {
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case PAGE_CACHE_WB:
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atomctl >>= 2;
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/* fall through */
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case PAGE_CACHE_WT:
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atomctl >>= 2;
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/* fall through */
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case PAGE_CACHE_BYPASS:
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if ((atomctl & 0x3) == 0) {
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HELPER(exception_cause_vaddr)(env, pc,
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@ -305,16 +305,21 @@ static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
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tcg_temp_free(tmp);
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}
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static void gen_advance_ccount(DisasContext *dc)
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static void gen_advance_ccount_cond(DisasContext *dc)
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{
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if (dc->ccount_delta > 0) {
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TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta);
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dc->ccount_delta = 0;
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gen_helper_advance_ccount(cpu_env, tmp);
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tcg_temp_free(tmp);
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}
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}
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static void gen_advance_ccount(DisasContext *dc)
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{
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gen_advance_ccount_cond(dc);
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dc->ccount_delta = 0;
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}
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static void reset_used_window(DisasContext *dc)
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{
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dc->used_window = 0;
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@ -491,7 +496,7 @@ static void gen_brcondi(DisasContext *dc, TCGCond cond,
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tcg_temp_free(tmp);
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}
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static void gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
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static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
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{
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if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) {
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if (sregnames[sr].name) {
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@ -500,6 +505,7 @@ static void gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
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qemu_log("SR %d is not implemented\n", sr);
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}
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gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
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return false;
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} else if (!(sregnames[sr].access & access)) {
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static const char * const access_text[] = {
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[SR_R] = "rsr",
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@ -510,7 +516,9 @@ static void gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
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qemu_log("SR %s is not available for %s\n", sregnames[sr].name,
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access_text[access]);
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gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
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return false;
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}
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return true;
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}
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static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
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@ -826,15 +834,27 @@ static void gen_window_check1(DisasContext *dc, unsigned r1)
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}
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if (option_enabled(dc, XTENSA_OPTION_WINDOWED_REGISTER) &&
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r1 / 4 > dc->used_window) {
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TCGv_i32 pc = tcg_const_i32(dc->pc);
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TCGv_i32 w = tcg_const_i32(r1 / 4);
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int label = gen_new_label();
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TCGv_i32 ws = tcg_temp_new_i32();
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dc->used_window = r1 / 4;
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gen_advance_ccount(dc);
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gen_helper_window_check(cpu_env, pc, w);
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tcg_gen_deposit_i32(ws, cpu_SR[WINDOW_START], cpu_SR[WINDOW_START],
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dc->config->nareg / 4, dc->config->nareg / 4);
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tcg_gen_shr_i32(ws, ws, cpu_SR[WINDOW_BASE]);
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tcg_gen_andi_i32(ws, ws, (2 << (r1 / 4)) - 2);
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tcg_gen_brcondi_i32(TCG_COND_EQ, ws, 0, label);
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{
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TCGv_i32 pc = tcg_const_i32(dc->pc);
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TCGv_i32 w = tcg_const_i32(r1 / 4);
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tcg_temp_free(w);
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tcg_temp_free(pc);
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gen_advance_ccount_cond(dc);
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gen_helper_window_check(cpu_env, pc, w);
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tcg_temp_free(w);
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tcg_temp_free(pc);
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}
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gen_set_label(label);
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tcg_temp_free(ws);
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}
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}
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@ -1482,9 +1502,9 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
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break;
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case 6: /*XSR*/
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{
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if (gen_check_sr(dc, RSR_SR, SR_X)) {
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TCGv_i32 tmp = tcg_temp_new_i32();
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gen_check_sr(dc, RSR_SR, SR_X);
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if (RSR_SR >= 64) {
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gen_check_privilege(dc);
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}
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@ -1707,21 +1727,23 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
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case 3: /*RST3*/
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switch (OP2) {
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case 0: /*RSR*/
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gen_check_sr(dc, RSR_SR, SR_R);
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if (RSR_SR >= 64) {
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gen_check_privilege(dc);
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if (gen_check_sr(dc, RSR_SR, SR_R)) {
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if (RSR_SR >= 64) {
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gen_check_privilege(dc);
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}
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gen_window_check1(dc, RRR_T);
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gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
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}
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gen_window_check1(dc, RRR_T);
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gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
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break;
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case 1: /*WSR*/
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gen_check_sr(dc, RSR_SR, SR_W);
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if (RSR_SR >= 64) {
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gen_check_privilege(dc);
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if (gen_check_sr(dc, RSR_SR, SR_W)) {
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if (RSR_SR >= 64) {
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gen_check_privilege(dc);
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}
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gen_window_check1(dc, RRR_T);
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gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
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}
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gen_window_check1(dc, RRR_T);
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gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
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break;
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case 2: /*SEXTu*/
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@ -2918,8 +2940,7 @@ void gen_intermediate_code_internal(XtensaCPU *cpu,
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gen_tb_start();
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if (cs->singlestep_enabled && env->exception_taken) {
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env->exception_taken = 0;
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if (tb->flags & XTENSA_TBFLAG_EXCEPTION) {
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tcg_gen_movi_i32(cpu_pc, dc.pc);
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gen_exception(&dc, EXCP_DEBUG);
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}
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