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target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode
In the ARM ldr/str decode path, rather than directly testing "insn & (1 << 21)" and "insn & (1 << 24)", abstract these bits out into wbit and pbit local flags. (We will want to do more tests against them to determine whether we need to provide syndrome information.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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1 changed files with 6 additions and 3 deletions
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@ -8782,6 +8782,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
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} else {
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} else {
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int address_offset;
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int address_offset;
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bool load = insn & (1 << 20);
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bool load = insn & (1 << 20);
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bool wbit = insn & (1 << 21);
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bool pbit = insn & (1 << 24);
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bool doubleword = false;
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bool doubleword = false;
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/* Misc load/store */
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/* Misc load/store */
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rn = (insn >> 16) & 0xf;
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rn = (insn >> 16) & 0xf;
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@ -8799,8 +8801,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
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}
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}
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addr = load_reg(s, rn);
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addr = load_reg(s, rn);
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if (insn & (1 << 24))
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if (pbit) {
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gen_add_datah_offset(s, insn, 0, addr);
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gen_add_datah_offset(s, insn, 0, addr);
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}
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address_offset = 0;
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address_offset = 0;
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if (doubleword) {
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if (doubleword) {
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@ -8849,10 +8852,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
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ensure correct behavior with overlapping index registers.
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ensure correct behavior with overlapping index registers.
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ldrd with base writeback is undefined if the
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ldrd with base writeback is undefined if the
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destination and index registers overlap. */
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destination and index registers overlap. */
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if (!(insn & (1 << 24))) {
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if (!pbit) {
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gen_add_datah_offset(s, insn, address_offset, addr);
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gen_add_datah_offset(s, insn, address_offset, addr);
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store_reg(s, rn, addr);
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store_reg(s, rn, addr);
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} else if (insn & (1 << 21)) {
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} else if (wbit) {
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if (address_offset)
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if (address_offset)
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tcg_gen_addi_i32(addr, addr, address_offset);
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tcg_gen_addi_i32(addr, addr, address_offset);
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store_reg(s, rn, addr);
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store_reg(s, rn, addr);
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