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Misc HW patch queue

Browse source 
- Deprecate a pair of untested microblaze big-endian machines (Philippe)
 - Arch-agnostic CPU topology checks at machine level (Zhao)
 - Cleanups on PPC E500 (Bernhard)
 - Various conversions to DEFINE_TYPES() macro (Bernhard)
 - Fix RISC-V _pext_u64() name clashing (Pierrick)
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Merge tag 'hw-misc-20241105' of https://github.com/philmd/qemu into staging

Misc HW patch queue

- Deprecate a pair of untested microblaze big-endian machines (Philippe)
- Arch-agnostic CPU topology checks at machine level (Zhao)
- Cleanups on PPC E500 (Bernhard)
- Various conversions to DEFINE_TYPES() macro (Bernhard)
- Fix RISC-V _pext_u64() name clashing (Pierrick)

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# gpg: Signature made Tue 05 Nov 2024 23:32:55 GMT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'hw-misc-20241105' of https://github.com/philmd/qemu: (29 commits)
  hw/riscv/iommu: fix build error with clang
  hw/usb/hcd-ehci-sysbus: Prefer DEFINE_TYPES() macro
  hw/rtc/ds1338: Prefer DEFINE_TYPES() macro
  hw/i2c/smbus_eeprom: Prefer DEFINE_TYPES() macro
  hw/block/pflash_cfi01: Prefer DEFINE_TYPES() macro
  hw/sd/sdhci: Prefer DEFINE_TYPES() macro
  hw/ppc/mpc8544_guts: Prefer DEFINE_TYPES() macro
  hw/gpio/mpc8xxx: Prefer DEFINE_TYPES() macro
  hw/net/fsl_etsec/etsec: Prefer DEFINE_TYPES() macro
  hw/net/fsl_etsec/miim: Reuse MII constants
  hw/pci-host/ppce500: Prefer DEFINE_TYPES() macro
  hw/pci-host/ppce500: Reuse TYPE_PPC_E500_PCI_BRIDGE define
  hw/i2c/mpc_i2c: Prefer DEFINE_TYPES() macro
  hw/i2c/mpc_i2c: Convert DPRINTF to trace events for register access
  hw/ppc/mpc8544_guts: Populate POR PLL ratio status register
  hw/ppc/e500: Add missing device tree properties to i2c controller node
  hw/ppc/e500: Remove unused "irqs" parameter
  hw/ppc/e500: Prefer QOM cast
  hw/core: Add a helper to check the cache topology level
  hw/core: Check smp cache topology support for machine
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2024-11-06 17:28:45 +00:00
commit 63dc369443
29 changed files with 625 additions and 347 deletions
Download patch file Download diff file Expand all files Collapse all files

151
target/i386/cpu.c
View file

@ -238,23 +238,23 @@ static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
0 /* Invalid value */)
static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info,
enum CPUTopoLevel share_level)
enum CpuTopologyLevel share_level)
{
uint32_t num_ids = 0;
switch (share_level) {
case CPU_TOPO_LEVEL_CORE:
case CPU_TOPOLOGY_LEVEL_CORE:
num_ids = 1 << apicid_core_offset(topo_info);
break;
case CPU_TOPO_LEVEL_DIE:
case CPU_TOPOLOGY_LEVEL_DIE:
num_ids = 1 << apicid_die_offset(topo_info);
break;
case CPU_TOPO_LEVEL_PACKAGE:
case CPU_TOPOLOGY_LEVEL_SOCKET:
num_ids = 1 << apicid_pkg_offset(topo_info);
break;
default:
/*
* Currently there is no use case for SMT and MODULE, so use
* Currently there is no use case for THREAD and MODULE, so use
* assert directly to facilitate debugging.
*/
g_assert_not_reached();
@ -303,19 +303,19 @@ static void encode_cache_cpuid4(CPUCacheInfo *cache,
}
static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info,
enum CPUTopoLevel topo_level)
enum CpuTopologyLevel topo_level)
{
switch (topo_level) {
case CPU_TOPO_LEVEL_SMT:
case CPU_TOPOLOGY_LEVEL_THREAD:
return 1;
case CPU_TOPO_LEVEL_CORE:
case CPU_TOPOLOGY_LEVEL_CORE:
return topo_info->threads_per_core;
case CPU_TOPO_LEVEL_MODULE:
case CPU_TOPOLOGY_LEVEL_MODULE:
return topo_info->threads_per_core * topo_info->cores_per_module;
case CPU_TOPO_LEVEL_DIE:
case CPU_TOPOLOGY_LEVEL_DIE:
return topo_info->threads_per_core * topo_info->cores_per_module *
topo_info->modules_per_die;
case CPU_TOPO_LEVEL_PACKAGE:
case CPU_TOPOLOGY_LEVEL_SOCKET:
return topo_info->threads_per_core * topo_info->cores_per_module *
topo_info->modules_per_die * topo_info->dies_per_pkg;
default:
@ -325,18 +325,18 @@ static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info,
}
static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info,
enum CPUTopoLevel topo_level)
enum CpuTopologyLevel topo_level)
{
switch (topo_level) {
case CPU_TOPO_LEVEL_SMT:
case CPU_TOPOLOGY_LEVEL_THREAD:
return 0;
case CPU_TOPO_LEVEL_CORE:
case CPU_TOPOLOGY_LEVEL_CORE:
return apicid_core_offset(topo_info);
case CPU_TOPO_LEVEL_MODULE:
case CPU_TOPOLOGY_LEVEL_MODULE:
return apicid_module_offset(topo_info);
case CPU_TOPO_LEVEL_DIE:
case CPU_TOPOLOGY_LEVEL_DIE:
return apicid_die_offset(topo_info);
case CPU_TOPO_LEVEL_PACKAGE:
case CPU_TOPOLOGY_LEVEL_SOCKET:
return apicid_pkg_offset(topo_info);
default:
g_assert_not_reached();
@ -344,18 +344,18 @@ static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info,
return 0;
}
static uint32_t cpuid1f_topo_type(enum CPUTopoLevel topo_level)
static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level)
{
switch (topo_level) {
case CPU_TOPO_LEVEL_INVALID:
case CPU_TOPOLOGY_LEVEL_INVALID:
return CPUID_1F_ECX_TOPO_LEVEL_INVALID;
case CPU_TOPO_LEVEL_SMT:
case CPU_TOPOLOGY_LEVEL_THREAD:
return CPUID_1F_ECX_TOPO_LEVEL_SMT;
case CPU_TOPO_LEVEL_CORE:
case CPU_TOPOLOGY_LEVEL_CORE:
return CPUID_1F_ECX_TOPO_LEVEL_CORE;
case CPU_TOPO_LEVEL_MODULE:
case CPU_TOPOLOGY_LEVEL_MODULE:
return CPUID_1F_ECX_TOPO_LEVEL_MODULE;
case CPU_TOPO_LEVEL_DIE:
case CPU_TOPOLOGY_LEVEL_DIE:
return CPUID_1F_ECX_TOPO_LEVEL_DIE;
default:
/* Other types are not supported in QEMU. */
@ -370,38 +370,41 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count,
uint32_t *ecx, uint32_t *edx)
{
X86CPU *cpu = env_archcpu(env);
unsigned long level, next_level;
unsigned long level, base_level, next_level;
uint32_t num_threads_next_level, offset_next_level;
assert(count + 1 < CPU_TOPO_LEVEL_MAX);
assert(count <= CPU_TOPOLOGY_LEVEL_SOCKET);
/*
* Find the No.(count + 1) topology level in avail_cpu_topo bitmap.
* The search starts from bit 1 (CPU_TOPO_LEVEL_INVALID + 1).
* The search starts from bit 0 (CPU_TOPOLOGY_LEVEL_THREAD).
*/
level = CPU_TOPO_LEVEL_INVALID;
level = CPU_TOPOLOGY_LEVEL_THREAD;
base_level = level;
for (int i = 0; i <= count; i++) {
level = find_next_bit(env->avail_cpu_topo,
CPU_TOPO_LEVEL_PACKAGE,
level + 1);
CPU_TOPOLOGY_LEVEL_SOCKET,
base_level);
/*
* CPUID[0x1f] doesn't explicitly encode the package level,
* and it just encodes the invalid level (all fields are 0)
* into the last subleaf of 0x1f.
*/
if (level == CPU_TOPO_LEVEL_PACKAGE) {
level = CPU_TOPO_LEVEL_INVALID;
if (level == CPU_TOPOLOGY_LEVEL_SOCKET) {
level = CPU_TOPOLOGY_LEVEL_INVALID;
break;
}
/* Search the next level. */
base_level = level + 1;
}
if (level == CPU_TOPO_LEVEL_INVALID) {
if (level == CPU_TOPOLOGY_LEVEL_INVALID) {
num_threads_next_level = 0;
offset_next_level = 0;
} else {
next_level = find_next_bit(env->avail_cpu_topo,
CPU_TOPO_LEVEL_PACKAGE,
CPU_TOPOLOGY_LEVEL_SOCKET,
level + 1);
num_threads_next_level = num_threads_by_topo_level(topo_info,
next_level);
@ -577,7 +580,7 @@ static CPUCacheInfo legacy_l1d_cache = {
.sets = 64,
.partitions = 1,
.no_invd_sharing = true,
.share_level = CPU_TOPO_LEVEL_CORE,
.share_level = CPU_TOPOLOGY_LEVEL_CORE,
};
/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
@ -592,7 +595,7 @@ static CPUCacheInfo legacy_l1d_cache_amd = {
.partitions = 1,
.lines_per_tag = 1,
.no_invd_sharing = true,
.share_level = CPU_TOPO_LEVEL_CORE,
.share_level = CPU_TOPOLOGY_LEVEL_CORE,
};
/* L1 instruction cache: */
@ -606,7 +609,7 @@ static CPUCacheInfo legacy_l1i_cache = {
.sets = 64,
.partitions = 1,
.no_invd_sharing = true,
.share_level = CPU_TOPO_LEVEL_CORE,
.share_level = CPU_TOPOLOGY_LEVEL_CORE,
};
/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
@ -621,7 +624,7 @@ static CPUCacheInfo legacy_l1i_cache_amd = {
.partitions = 1,
.lines_per_tag = 1,
.no_invd_sharing = true,
.share_level = CPU_TOPO_LEVEL_CORE,
.share_level = CPU_TOPOLOGY_LEVEL_CORE,
};
/* Level 2 unified cache: */
@ -635,7 +638,7 @@ static CPUCacheInfo legacy_l2_cache = {
.sets = 4096,
.partitions = 1,
.no_invd_sharing = true,
.share_level = CPU_TOPO_LEVEL_CORE,
.share_level = CPU_TOPOLOGY_LEVEL_CORE,
};
/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
@ -645,7 +648,7 @@ static CPUCacheInfo legacy_l2_cache_cpuid2 = {
.size = 2 * MiB,
.line_size = 64,
.associativity = 8,
.share_level = CPU_TOPO_LEVEL_INVALID,
.share_level = CPU_TOPOLOGY_LEVEL_INVALID,
};
@ -659,7 +662,7 @@ static CPUCacheInfo legacy_l2_cache_amd = {
.associativity = 16,
.sets = 512,
.partitions = 1,
.share_level = CPU_TOPO_LEVEL_CORE,
.share_level = CPU_TOPOLOGY_LEVEL_CORE,
};
/* Level 3 unified cache: */
@ -675,7 +678,7 @@ static CPUCacheInfo legacy_l3_cache = {
.self_init = true,
.inclusive = true,
.complex_indexing = true,
.share_level = CPU_TOPO_LEVEL_DIE,
.share_level = CPU_TOPOLOGY_LEVEL_DIE,
};
/* TLB definitions: */
@ -2082,7 +2085,7 @@ static const CPUCaches epyc_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
.share_level = CPU_TOPO_LEVEL_CORE,
.share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l1i_cache = &(CPUCacheInfo) {
.type = INSTRUCTION_CACHE,
@ -2095,7 +2098,7 @@ static const CPUCaches epyc_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
.share_level = CPU_TOPO_LEVEL_CORE,
.share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l2_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@ -2106,7 +2109,7 @@ static const CPUCaches epyc_cache_info = {
.partitions = 1,
.sets = 1024,
.lines_per_tag = 1,
.share_level = CPU_TOPO_LEVEL_CORE,
.share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l3_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@ -2120,7 +2123,7 @@ static const CPUCaches epyc_cache_info = {
.self_init = true,
.inclusive = true,
.complex_indexing = true,
.share_level = CPU_TOPO_LEVEL_DIE,
.share_level = CPU_TOPOLOGY_LEVEL_DIE,
},
};
@ -2136,7 +2139,7 @@ static CPUCaches epyc_v4_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
.share_level = CPU_TOPO_LEVEL_CORE,
.share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l1i_cache = &(CPUCacheInfo) {
.type = INSTRUCTION_CACHE,
@ -2149,7 +2152,7 @@ static CPUCaches epyc_v4_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
.share_level = CPU_TOPO_LEVEL_CORE,
.share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l2_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@ -2160,7 +2163,7 @@ static CPUCaches epyc_v4_cache_info = {
.partitions = 1,
.sets = 1024,
.lines_per_tag = 1,
.share_level = CPU_TOPO_LEVEL_CORE,
.share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l3_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@ -2174,7 +2177,7 @@ static CPUCaches epyc_v4_cache_info = {
.self_init = true,
.inclusive = true,
.complex_indexing = false,
.share_level = CPU_TOPO_LEVEL_DIE,
.share_level = CPU_TOPOLOGY_LEVEL_DIE,
},
};
@ -2190,7 +2193,7 @@ static const CPUCaches epyc_rome_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
.share_level = CPU_TOPO_LEVEL_CORE,
.share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l1i_cache = &(CPUCacheInfo) {
.type = INSTRUCTION_CACHE,
@ -2203,7 +2206,7 @@ static const CPUCaches epyc_rome_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
.share_level = CPU_TOPO_LEVEL_CORE,
.share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l2_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@ -2214,7 +2217,7 @@ static const CPUCaches epyc_rome_cache_info = {
.partitions = 1,
.sets = 1024,
.lines_per_tag = 1,
.share_level = CPU_TOPO_LEVEL_CORE,
.share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l3_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@ -2228,7 +2231,7 @@ static const CPUCaches epyc_rome_cache_info = {
.self_init = true,
.inclusive = true,
.complex_indexing = true,
.share_level = CPU_TOPO_LEVEL_DIE,
.share_level = CPU_TOPOLOGY_LEVEL_DIE,
},
};
@ -2244,7 +2247,7 @@ static const CPUCaches epyc_rome_v3_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
.share_level = CPU_TOPO_LEVEL_CORE,
.share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l1i_cache = &(CPUCacheInfo) {
.type = INSTRUCTION_CACHE,
@ -2257,7 +2260,7 @@ static const CPUCaches epyc_rome_v3_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
.share_level = CPU_TOPO_LEVEL_CORE,
.share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l2_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@ -2268,7 +2271,7 @@ static const CPUCaches epyc_rome_v3_cache_info = {
.partitions = 1,
.sets = 1024,
.lines_per_tag = 1,
.share_level = CPU_TOPO_LEVEL_CORE,
.share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l3_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@ -2282,7 +2285,7 @@ static const CPUCaches epyc_rome_v3_cache_info = {
.self_init = true,
.inclusive = true,
.complex_indexing = false,
.share_level = CPU_TOPO_LEVEL_DIE,
.share_level = CPU_TOPOLOGY_LEVEL_DIE,
},
};
@ -2298,7 +2301,7 @@ static const CPUCaches epyc_milan_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
.share_level = CPU_TOPO_LEVEL_CORE,
.share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l1i_cache = &(CPUCacheInfo) {
.type = INSTRUCTION_CACHE,
@ -2311,7 +2314,7 @@ static const CPUCaches epyc_milan_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
.share_level = CPU_TOPO_LEVEL_CORE,
.share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l2_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@ -2322,7 +2325,7 @@ static const CPUCaches epyc_milan_cache_info = {
.partitions = 1,
.sets = 1024,
.lines_per_tag = 1,
.share_level = CPU_TOPO_LEVEL_CORE,
.share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l3_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@ -2336,7 +2339,7 @@ static const CPUCaches epyc_milan_cache_info = {
.self_init = true,
.inclusive = true,
.complex_indexing = true,
.share_level = CPU_TOPO_LEVEL_DIE,
.share_level = CPU_TOPOLOGY_LEVEL_DIE,
},
};
@ -2352,7 +2355,7 @@ static const CPUCaches epyc_milan_v2_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
.share_level = CPU_TOPO_LEVEL_CORE,
.share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l1i_cache = &(CPUCacheInfo) {
.type = INSTRUCTION_CACHE,
@ -2365,7 +2368,7 @@ static const CPUCaches epyc_milan_v2_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
.share_level = CPU_TOPO_LEVEL_CORE,
.share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l2_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@ -2376,7 +2379,7 @@ static const CPUCaches epyc_milan_v2_cache_info = {
.partitions = 1,
.sets = 1024,
.lines_per_tag = 1,
.share_level = CPU_TOPO_LEVEL_CORE,
.share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l3_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@ -2390,7 +2393,7 @@ static const CPUCaches epyc_milan_v2_cache_info = {
.self_init = true,
.inclusive = true,
.complex_indexing = false,
.share_level = CPU_TOPO_LEVEL_DIE,
.share_level = CPU_TOPOLOGY_LEVEL_DIE,
},
};
@ -2406,7 +2409,7 @@ static const CPUCaches epyc_genoa_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
.share_level = CPU_TOPO_LEVEL_CORE,
.share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l1i_cache = &(CPUCacheInfo) {
.type = INSTRUCTION_CACHE,
@ -2419,7 +2422,7 @@ static const CPUCaches epyc_genoa_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
.share_level = CPU_TOPO_LEVEL_CORE,
.share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l2_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@ -2430,7 +2433,7 @@ static const CPUCaches epyc_genoa_cache_info = {
.partitions = 1,
.sets = 2048,
.lines_per_tag = 1,
.share_level = CPU_TOPO_LEVEL_CORE,
.share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l3_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@ -2444,7 +2447,7 @@ static const CPUCaches epyc_genoa_cache_info = {
.self_init = true,
.inclusive = true,
.complex_indexing = false,
.share_level = CPU_TOPO_LEVEL_DIE,
.share_level = CPU_TOPOLOGY_LEVEL_DIE,
},
};
@ -6588,7 +6591,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
/* Share the cache at package level. */
*eax |= max_thread_ids_for_cache(&topo_info,
CPU_TOPO_LEVEL_PACKAGE) << 14;
CPU_TOPOLOGY_LEVEL_SOCKET) << 14;
}
}
} else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) {
@ -8170,10 +8173,10 @@ static void x86_cpu_init_default_topo(X86CPU *cpu)
env->nr_modules = 1;
env->nr_dies = 1;
/* SMT, core and package levels are set by default. */
set_bit(CPU_TOPO_LEVEL_SMT, env->avail_cpu_topo);
set_bit(CPU_TOPO_LEVEL_CORE, env->avail_cpu_topo);
set_bit(CPU_TOPO_LEVEL_PACKAGE, env->avail_cpu_topo);
/* thread, core and socket levels are set by default. */
set_bit(CPU_TOPOLOGY_LEVEL_THREAD, env->avail_cpu_topo);
set_bit(CPU_TOPOLOGY_LEVEL_CORE, env->avail_cpu_topo);
set_bit(CPU_TOPOLOGY_LEVEL_SOCKET, env->avail_cpu_topo);
}
static void x86_cpu_initfn(Object *obj)

4
target/i386/cpu.h
View file

@ -1716,7 +1716,7 @@ typedef struct CPUCacheInfo {
* Used to encode CPUID[4].EAX[bits 25:14] or
* CPUID[0x8000001D].EAX[bits 25:14].
*/
enum CPUTopoLevel share_level;
CpuTopologyLevel share_level;
} CPUCacheInfo;
@ -2051,7 +2051,7 @@ typedef struct CPUArchState {
unsigned nr_modules;
/* Bitmap of available CPU topology levels for this CPU. */
DECLARE_BITMAP(avail_cpu_topo, CPU_TOPO_LEVEL_MAX);
DECLARE_BITMAP(avail_cpu_topo, CPU_TOPOLOGY_LEVEL__MAX);
} CPUX86State;
struct kvm_msrs;

10
target/microblaze/cpu.c
View file

@ -332,9 +332,16 @@ static void mb_cpu_initfn(Object *obj)
qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dc, "ns_axi_dc", 1);
qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ic, "ns_axi_ic", 1);
#endif
/* Restricted 'endianness' property is equivalent of 'little-endian' */
object_property_add_alias(obj, "little-endian", obj, "endianness");
}
static Property mb_properties[] = {
/*
* Following properties are used by Xilinx DTS conversion tool
* do not rename them.
*/
DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
false),
@ -391,6 +398,9 @@ static Property mb_properties[] = {
DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0),
DEFINE_PROP_UINT32("pvr-user2", MicroBlazeCPU, cfg.pvr_user2, 0),
/*
* End of properties reserved by Xilinx DTS conversion tool.
*/
DEFINE_PROP_END_OF_LIST(),
};