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Misc HW patch queue
- Deprecate a pair of untested microblaze big-endian machines (Philippe) - Arch-agnostic CPU topology checks at machine level (Zhao) - Cleanups on PPC E500 (Bernhard) - Various conversions to DEFINE_TYPES() macro (Bernhard) - Fix RISC-V _pext_u64() name clashing (Pierrick) -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmcqqycACgkQ4+MsLN6t wN7TfhAAkAjpWxFGptNw28LPpnZY/NTGKyXQrIEHu3XnJsZ28c/KZeCAYUUC6/q7 tAnBMb5GIn2VTyt+ElORseFtHStThoR8WMrcQSlGvCZei9lRNKCW0pVIEUgLZEtT u8lChpaVAn8gXb885xlaCBBP4SuFHEpASSfWy0mYDIqZL3oRhr9AQ/KwzHFqenbK Uva4BCWRVnYju6MhfA/pmVP011SUTdCu/fsBTIJT3Xn7Sp7fRNShIzt+1rbmPnR2 hhRl5bMKUgDUjX5GxeP0LOj/XdX9svlqL42imNQT5FFUMIR6qbrwj4U841mt0uuI FcthAoILvA2XUJoTESq0iXUoN4FQLtc01onY6k06EoZAnn8WRZRp2dNdu8fYmHMX y3pcXBK6wEhBVZ2DcGVf1txmieUc4TZohOridU1Xfckp+XVl6J3LtTKJIE56Eh68 S9OJW1Sz2Io/8FJFvKStX0bhV0nBUyUXmi5PjV4vurS6Gy1aVodiiq3ls6baX05z /Y8DJGpPByA+GI2prdwq9oTIhEIU2bJDDz32NkwHM99SE25h+iyh21Ap5Ojkegm7 1squIskxX3QLtEMxBCe+XIKzEZ51kzNZxmLXvCFW5YetypNdhyULqH/UDWt7hIDN BSh2w1g/lSw9n6DtEN3rURYAR/uV7/7IMEP8Td2wvcDX4o95Fkw= =q0cF -----END PGP SIGNATURE----- Merge tag 'hw-misc-20241105' of https://github.com/philmd/qemu into staging Misc HW patch queue - Deprecate a pair of untested microblaze big-endian machines (Philippe) - Arch-agnostic CPU topology checks at machine level (Zhao) - Cleanups on PPC E500 (Bernhard) - Various conversions to DEFINE_TYPES() macro (Bernhard) - Fix RISC-V _pext_u64() name clashing (Pierrick) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmcqqycACgkQ4+MsLN6t # wN7TfhAAkAjpWxFGptNw28LPpnZY/NTGKyXQrIEHu3XnJsZ28c/KZeCAYUUC6/q7 # tAnBMb5GIn2VTyt+ElORseFtHStThoR8WMrcQSlGvCZei9lRNKCW0pVIEUgLZEtT # u8lChpaVAn8gXb885xlaCBBP4SuFHEpASSfWy0mYDIqZL3oRhr9AQ/KwzHFqenbK # Uva4BCWRVnYju6MhfA/pmVP011SUTdCu/fsBTIJT3Xn7Sp7fRNShIzt+1rbmPnR2 # hhRl5bMKUgDUjX5GxeP0LOj/XdX9svlqL42imNQT5FFUMIR6qbrwj4U841mt0uuI # FcthAoILvA2XUJoTESq0iXUoN4FQLtc01onY6k06EoZAnn8WRZRp2dNdu8fYmHMX # y3pcXBK6wEhBVZ2DcGVf1txmieUc4TZohOridU1Xfckp+XVl6J3LtTKJIE56Eh68 # S9OJW1Sz2Io/8FJFvKStX0bhV0nBUyUXmi5PjV4vurS6Gy1aVodiiq3ls6baX05z # /Y8DJGpPByA+GI2prdwq9oTIhEIU2bJDDz32NkwHM99SE25h+iyh21Ap5Ojkegm7 # 1squIskxX3QLtEMxBCe+XIKzEZ51kzNZxmLXvCFW5YetypNdhyULqH/UDWt7hIDN # BSh2w1g/lSw9n6DtEN3rURYAR/uV7/7IMEP8Td2wvcDX4o95Fkw= # =q0cF # -----END PGP SIGNATURE----- # gpg: Signature made Tue 05 Nov 2024 23:32:55 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'hw-misc-20241105' of https://github.com/philmd/qemu: (29 commits) hw/riscv/iommu: fix build error with clang hw/usb/hcd-ehci-sysbus: Prefer DEFINE_TYPES() macro hw/rtc/ds1338: Prefer DEFINE_TYPES() macro hw/i2c/smbus_eeprom: Prefer DEFINE_TYPES() macro hw/block/pflash_cfi01: Prefer DEFINE_TYPES() macro hw/sd/sdhci: Prefer DEFINE_TYPES() macro hw/ppc/mpc8544_guts: Prefer DEFINE_TYPES() macro hw/gpio/mpc8xxx: Prefer DEFINE_TYPES() macro hw/net/fsl_etsec/etsec: Prefer DEFINE_TYPES() macro hw/net/fsl_etsec/miim: Reuse MII constants hw/pci-host/ppce500: Prefer DEFINE_TYPES() macro hw/pci-host/ppce500: Reuse TYPE_PPC_E500_PCI_BRIDGE define hw/i2c/mpc_i2c: Prefer DEFINE_TYPES() macro hw/i2c/mpc_i2c: Convert DPRINTF to trace events for register access hw/ppc/mpc8544_guts: Populate POR PLL ratio status register hw/ppc/e500: Add missing device tree properties to i2c controller node hw/ppc/e500: Remove unused "irqs" parameter hw/ppc/e500: Prefer QOM cast hw/core: Add a helper to check the cache topology level hw/core: Check smp cache topology support for machine ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
63dc369443
29 changed files with 625 additions and 347 deletions
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@ -44,8 +44,16 @@ void machine_set_cpu_numa_node(MachineState *machine,
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Error **errp);
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void machine_parse_smp_config(MachineState *ms,
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const SMPConfiguration *config, Error **errp);
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bool machine_parse_smp_cache(MachineState *ms,
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const SmpCachePropertiesList *caches,
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Error **errp);
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unsigned int machine_topo_get_cores_per_socket(const MachineState *ms);
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unsigned int machine_topo_get_threads_per_socket(const MachineState *ms);
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CpuTopologyLevel machine_get_cache_topo_level(const MachineState *ms,
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CacheLevelAndType cache);
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void machine_set_cache_topo_level(MachineState *ms, CacheLevelAndType cache,
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CpuTopologyLevel level);
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bool machine_check_smp_cache(const MachineState *ms, Error **errp);
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void machine_memory_devices_init(MachineState *ms, hwaddr base, uint64_t size);
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/**
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@ -146,6 +154,8 @@ typedef struct {
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* @books_supported - whether books are supported by the machine
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* @drawers_supported - whether drawers are supported by the machine
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* @modules_supported - whether modules are supported by the machine
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* @cache_supported - whether cache (l1d, l1i, l2 and l3) configuration are
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* supported by the machine
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*/
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typedef struct {
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bool prefer_sockets;
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@ -155,6 +165,7 @@ typedef struct {
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bool books_supported;
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bool drawers_supported;
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bool modules_supported;
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bool cache_supported[CACHE_LEVEL_AND_TYPE__MAX];
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} SMPCompatProps;
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/**
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@ -371,6 +382,10 @@ typedef struct CpuTopology {
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unsigned int max_cpus;
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} CpuTopology;
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typedef struct SmpCache {
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SmpCacheProperties props[CACHE_LEVEL_AND_TYPE__MAX];
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} SmpCache;
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/**
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* MachineState:
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*/
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@ -421,6 +436,7 @@ struct MachineState {
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AccelState *accelerator;
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CPUArchIdList *possible_cpus;
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CpuTopology smp;
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SmpCache smp_cache;
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struct NVDIMMState *nvdimms_state;
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struct NumaState *numa_state;
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};
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@ -39,7 +39,7 @@
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* CPUID Fn8000_0008_ECX[ApicIdCoreIdSize[3:0]] is set to apicid_core_width().
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*/
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#include "qapi/qapi-types-machine-common.h"
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#include "qemu/bitops.h"
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/*
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@ -62,21 +62,7 @@ typedef struct X86CPUTopoInfo {
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unsigned threads_per_core;
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} X86CPUTopoInfo;
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/*
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* CPUTopoLevel is the general i386 topology hierarchical representation,
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* ordered by increasing hierarchical relationship.
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* Its enumeration value is not bound to the type value of Intel (CPUID[0x1F])
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* or AMD (CPUID[0x80000026]).
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*/
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enum CPUTopoLevel {
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CPU_TOPO_LEVEL_INVALID,
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CPU_TOPO_LEVEL_SMT,
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CPU_TOPO_LEVEL_CORE,
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CPU_TOPO_LEVEL_MODULE,
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CPU_TOPO_LEVEL_DIE,
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CPU_TOPO_LEVEL_PACKAGE,
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CPU_TOPO_LEVEL_MAX,
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};
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#define CPU_TOPOLOGY_LEVEL_INVALID CPU_TOPOLOGY_LEVEL__MAX
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/* Return the bit width needed for 'count' IDs */
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static unsigned apicid_bitwidth_for_count(unsigned count)
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@ -212,8 +198,8 @@ static inline apic_id_t x86_apicid_from_cpu_idx(X86CPUTopoInfo *topo_info,
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*/
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static inline bool x86_has_extended_topo(unsigned long *topo_bitmap)
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{
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return test_bit(CPU_TOPO_LEVEL_MODULE, topo_bitmap) ||
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test_bit(CPU_TOPO_LEVEL_DIE, topo_bitmap);
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return test_bit(CPU_TOPOLOGY_LEVEL_MODULE, topo_bitmap) ||
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test_bit(CPU_TOPOLOGY_LEVEL_DIE, topo_bitmap);
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}
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#endif /* HW_I386_TOPOLOGY_H */
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