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intc/xilinx_intc: Don't clear level sens. IRQs without ACK
For level sensitive interrupts, ISR bits are cleared when the input pin is lowered. This is incorrect. Only software can clear ISR bits (via IAR or direct write to ISR with !MER(2)). Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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1 changed files with 1 additions and 7 deletions
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@ -135,13 +135,7 @@ static void irq_handler(void *opaque, int irq, int level)
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return;
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}
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/* Update source flops. Don't clear unless level triggered.
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Edge triggered interrupts only go away when explicitely acked to
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the interrupt controller. */
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if (!(p->c_kind_of_intr & (1 << irq)) || level) {
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p->regs[R_ISR] &= ~(1 << irq);
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p->regs[R_ISR] |= (level << irq);
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}
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p->regs[R_ISR] |= (level << irq);
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update_irq(p);
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}
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