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ppc/pnv: add a PIR handler to PnvChip
The Processor Identification Register (PIR) is a register that holds a processor identifier which is used for bus transactions (XSCOM) and for processor differentiation in multiprocessor systems. It also used in the interrupt vector entries (IVE) to identify the thread serving the interrupts. P9 and P8 have some differences in the CPU PIR encoding. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -58,6 +58,8 @@ typedef struct PnvChipClass {
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PnvChipType chip_type;
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uint64_t chip_cfam_id;
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uint64_t cores_mask;
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uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
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} PnvChipClass;
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#define TYPE_PNV_CHIP_POWER8E TYPE_PNV_CHIP "-POWER8E"
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