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target/riscv: Set [m|s]tval for both illegal and virtual instruction traps

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Currently, the [m|s]tval CSRs are set with trapping instruction encoding
only for illegal instruction traps taken at the time of instruction
decoding.

In RISC-V world, a valid instructions might also trap as illegal or
virtual instruction based to trapping bits in various CSRs (such as
mstatus.TVM or hstatus.VTVM).

We improve setting of [m|s]tval CSRs for all types of illegal and
virtual instruction traps.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220511144528.393530-4-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Anup Patel 2022-05-11 20:15:23 +05:30 • committed by Alistair Francis
parent 24826da0ee
commit 62cf02451e
4 changed files with 23 additions and 5 deletions
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8
target/riscv/cpu.h
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@ -30,6 +30,12 @@
#define TCG_GUEST_DEFAULT_MO 0
/*
* RISC-V-specific extra insn start words:
* 1: Original instruction opcode
*/
#define TARGET_INSN_START_EXTRA_WORDS 1
#define TYPE_RISCV_CPU "riscv-cpu"
#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
@ -140,7 +146,7 @@ struct CPUArchState {
target_ulong frm;
target_ulong badaddr;
uint32_t bins;
target_ulong bins;
target_ulong guest_phys_fault_addr;